board/freescale/imx8mp_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2018-2019, 2021 NXP
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <hang.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <spl.h>
  12 #include <asm/global_data.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx8mp_pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/arch/ddr.h>
  21 #include <power/pmic.h>
  22 #include <power/pca9450.h>
  23 #include <dm/uclass.h>
  24 #include <dm/device.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int spl_board_boot_device(enum boot_device boot_dev_spl)
  29 {
  30         return BOOT_DEVICE_BOOTROM;
  31 }
  32
  33 void spl_dram_init(void)
  34 {
  35         ddr_init(&dram_timing);
  36 }
  37
  38 void spl_board_init(void)
  39 {
  40         if (IS_ENABLED(CONFIG_FSL_CAAM)) {
  41                 struct udevice *dev;
  42                 int ret;
  43
  44                 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
  45                 if (ret)
  46                         printf("Failed to initialize caam_jr: %d\n", ret);
  47         }
  48         /*
  49          * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
  50          * not allow to change it. Should set the clock after PMIC
  51          * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
  52          * set by ROM for ND VDD_SOC
  53          */
  54         clock_enable(CCGR_GIC, 0);
  55         clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
  56         clock_enable(CCGR_GIC, 1);
  57
  58         puts("Normal Boot\n");
  59 }
  60
  61 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  62 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  63 struct i2c_pads_info i2c_pad_info1 = {
  64         .scl = {
  65                 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
  66                 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  67                 .gp = IMX_GPIO_NR(5, 14),
  68         },
  69         .sda = {
  70                 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
  71                 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  72                 .gp = IMX_GPIO_NR(5, 15),
  73         },
  74 };
  75
  76 #if CONFIG_IS_ENABLED(POWER_LEGACY)
  77 #define I2C_PMIC        0
  78 int power_init_board(void)
  79 {
  80         struct pmic *p;
  81         int ret;
  82
  83         ret = power_pca9450_init(I2C_PMIC, 0x25);
  84         if (ret)
  85                 printf("power init failed");
  86         p = pmic_get("PCA9450");
  87         pmic_probe(p);
  88
  89         /* BUCKxOUT_DVS0/1 control BUCK123 output */
  90         pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  91
  92         /*
  93          * increase VDD_SOC to typical value 0.95V before first
  94          * DRAM access, set DVS1 to 0.85v for suspend.
  95          * Enable DVS control through PMIC_STBY_REQ and
  96          * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
  97          */
  98 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
  99         /* set DVS0 to 0.85v for special case*/
 100         pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
 101 #else
 102         pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
 103 #endif
 104         pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
 105         pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
 106
 107         /* Kernel uses OD/OD freq for SOC */
 108         /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
 109         pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
 110
 111         /* set WDOG_B_CFG to cold reset */
 112         pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
 113
 114         return 0;
 115 }
 116 #endif
 117
 118 #ifdef CONFIG_SPL_LOAD_FIT
 119 int board_fit_config_name_match(const char *name)
 120 {
 121         /* Just empty function now - can't decide what to choose */
 122         debug("%s: %s\n", __func__, name);
 123
 124         return 0;
 125 }
 126 #endif
 127
 128 /* Do not use BSS area in this phase */
 129 void board_init_f(ulong dummy)
 130 {
 131         int ret;
 132
 133         arch_cpu_init();
 134
 135         init_uart_clk(1);
 136
 137         ret = spl_early_init();
 138         if (ret) {
 139                 debug("spl_init() failed: %d\n", ret);
 140                 hang();
 141         }
 142
 143         preloader_console_init();
 144
 145         enable_tzc380();
 146
 147         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 148
 149         power_init_board();
 150
 151         /* DDR initialization */
 152         spl_dram_init();
 153 }