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[thirdparty/u-boot.git] / board / freescale / imx8mp_evk / spl.c
1 /*
2 * Copyright 2018-2019 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <cpu_func.h>
10 #include <hang.h>
11 #include <image.h>
12 #include <init.h>
13 #include <spl.h>
14 #include <asm/io.h>
15 #include <errno.h>
16 #include <asm/io.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/arch/imx8mp_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <power/pmic.h>
22
23 #include <power/pca9450.h>
24 #include <asm/arch/clock.h>
25 #include <asm/mach-imx/gpio.h>
26 #include <asm/mach-imx/mxc_i2c.h>
27 #include <fsl_esdhc.h>
28 #include <mmc.h>
29 #include <asm/arch/ddr.h>
30
31 #include <dm/uclass.h>
32 #include <dm/device.h>
33 #include <dm/uclass-internal.h>
34 #include <dm/device-internal.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 int spl_board_boot_device(enum boot_device boot_dev_spl)
39 {
40 return BOOT_DEVICE_BOOTROM;
41 }
42
43 void spl_dram_init(void)
44 {
45 ddr_init(&dram_timing);
46 }
47
48 void spl_board_init(void)
49 {
50 struct udevice *dev;
51 int ret;
52
53 puts("Normal Boot\n");
54
55 ret = uclass_get_device_by_name(UCLASS_CLK,
56 "clock-controller@30380000",
57 &dev);
58 if (ret < 0)
59 printf("Failed to find clock node. Check device tree\n");
60 }
61
62 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
63 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
64 struct i2c_pads_info i2c_pad_info1 = {
65 .scl = {
66 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
67 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
68 .gp = IMX_GPIO_NR(5, 14),
69 },
70 .sda = {
71 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
72 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
73 .gp = IMX_GPIO_NR(5, 15),
74 },
75 };
76
77 #ifdef CONFIG_POWER
78 #define I2C_PMIC 0
79 int power_init_board(void)
80 {
81 struct pmic *p;
82 int ret;
83
84 ret = power_pca9450b_init(I2C_PMIC);
85 if (ret)
86 printf("power init failed");
87 p = pmic_get("PCA9450");
88 pmic_probe(p);
89
90 /* BUCKxOUT_DVS0/1 control BUCK123 output */
91 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
92
93 /*
94 * increase VDD_SOC to typical value 0.95V before first
95 * DRAM access, set DVS1 to 0.85v for suspend.
96 * Enable DVS control through PMIC_STBY_REQ and
97 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
98 */
99 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
100 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
101 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
102
103 /* set WDOG_B_CFG to cold reset */
104 pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
105
106 return 0;
107 }
108 #endif
109
110 #ifdef CONFIG_SPL_LOAD_FIT
111 int board_fit_config_name_match(const char *name)
112 {
113 /* Just empty function now - can't decide what to choose */
114 debug("%s: %s\n", __func__, name);
115
116 return 0;
117 }
118 #endif
119
120 void board_init_f(ulong dummy)
121 {
122 int ret;
123
124 arch_cpu_init();
125
126 init_uart_clk(1);
127
128 board_early_init_f();
129
130 timer_init();
131
132 preloader_console_init();
133
134 /* Clear the BSS. */
135 memset(__bss_start, 0, __bss_end - __bss_start);
136
137 ret = spl_init();
138 if (ret) {
139 debug("spl_init() failed: %d\n", ret);
140 hang();
141 }
142
143 enable_tzc380();
144
145 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
146
147 power_init_board();
148
149 /* DDR initialization */
150 spl_dram_init();
151
152 board_init_r(NULL, 0);
153 }