1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2019 NXP Semiconductors
5 #include <clock_legacy.h>
6 #include <fdt_support.h>
8 #include <asm/arch-ls102xa/ls102xa_soc.h>
9 #include <asm/arch/ls102xa_devdis.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ls102xa_soc.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include "../common/sleep.h"
14 #include <fsl_validate.h>
15 #include <fsl_immap.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 static void ddrmc_init(void)
27 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
28 struct ccsr_ddr
*ddr
= (struct ccsr_ddr
*)CONFIG_SYS_FSL_DDR_ADDR
;
29 u32 temp_sdram_cfg
, tmp
;
31 out_be32(&ddr
->sdram_cfg
, DDR_SDRAM_CFG
);
33 out_be32(&ddr
->cs0_bnds
, DDR_CS0_BNDS
);
34 out_be32(&ddr
->cs0_config
, DDR_CS0_CONFIG
);
36 out_be32(&ddr
->timing_cfg_0
, DDR_TIMING_CFG_0
);
37 out_be32(&ddr
->timing_cfg_1
, DDR_TIMING_CFG_1
);
38 out_be32(&ddr
->timing_cfg_2
, DDR_TIMING_CFG_2
);
39 out_be32(&ddr
->timing_cfg_3
, DDR_TIMING_CFG_3
);
40 out_be32(&ddr
->timing_cfg_4
, DDR_TIMING_CFG_4
);
41 out_be32(&ddr
->timing_cfg_5
, DDR_TIMING_CFG_5
);
43 #ifdef CONFIG_DEEP_SLEEP
45 out_be32(&ddr
->sdram_cfg_2
,
46 DDR_SDRAM_CFG_2
& ~SDRAM_CFG2_D_INIT
);
47 out_be32(&ddr
->init_addr
, CONFIG_SYS_SDRAM_BASE
);
48 out_be32(&ddr
->init_ext_addr
, (1 << 31));
50 /* DRAM VRef will not be trained */
51 out_be32(&ddr
->ddr_cdr2
,
52 DDR_DDR_CDR2
& ~DDR_CDR2_VREF_TRAIN_EN
);
56 out_be32(&ddr
->sdram_cfg_2
, DDR_SDRAM_CFG_2
);
57 out_be32(&ddr
->ddr_cdr2
, DDR_DDR_CDR2
);
60 out_be32(&ddr
->sdram_mode
, DDR_SDRAM_MODE
);
61 out_be32(&ddr
->sdram_mode_2
, DDR_SDRAM_MODE_2
);
63 out_be32(&ddr
->sdram_interval
, DDR_SDRAM_INTERVAL
);
65 out_be32(&ddr
->ddr_wrlvl_cntl
, DDR_DDR_WRLVL_CNTL
);
67 out_be32(&ddr
->ddr_wrlvl_cntl_2
, DDR_DDR_WRLVL_CNTL_2
);
68 out_be32(&ddr
->ddr_wrlvl_cntl_3
, DDR_DDR_WRLVL_CNTL_3
);
70 out_be32(&ddr
->ddr_cdr1
, DDR_DDR_CDR1
);
72 out_be32(&ddr
->sdram_clk_cntl
, DDR_SDRAM_CLK_CNTL
);
73 out_be32(&ddr
->ddr_zq_cntl
, DDR_DDR_ZQ_CNTL
);
75 out_be32(&ddr
->cs0_config_2
, DDR_CS0_CONFIG_2
);
77 /* DDR erratum A-009942 */
78 tmp
= in_be32(&ddr
->debug
[28]);
79 out_be32(&ddr
->debug
[28], tmp
| 0x0070006f);
83 #ifdef CONFIG_DEEP_SLEEP
85 /* enter self-refresh */
86 temp_sdram_cfg
= in_be32(&ddr
->sdram_cfg_2
);
87 temp_sdram_cfg
|= SDRAM_CFG2_FRC_SR
;
88 out_be32(&ddr
->sdram_cfg_2
, temp_sdram_cfg
);
90 temp_sdram_cfg
= (DDR_SDRAM_CFG_MEM_EN
| SDRAM_CFG_BI
);
93 temp_sdram_cfg
= (DDR_SDRAM_CFG_MEM_EN
& ~SDRAM_CFG_BI
);
95 out_be32(&ddr
->sdram_cfg
, DDR_SDRAM_CFG
| temp_sdram_cfg
);
97 #ifdef CONFIG_DEEP_SLEEP
99 /* exit self-refresh */
100 temp_sdram_cfg
= in_be32(&ddr
->sdram_cfg_2
);
101 temp_sdram_cfg
&= ~SDRAM_CFG2_FRC_SR
;
102 out_be32(&ddr
->sdram_cfg_2
, temp_sdram_cfg
);
105 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
112 erratum_a008850_post();
114 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM
, PHYS_SDRAM_SIZE
);
116 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
123 int board_eth_init(bd_t
*bis
)
125 return pci_eth_init(bis
);
128 int board_early_init_f(void)
130 struct ccsr_scfg
*scfg
= (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR
;
132 #ifdef CONFIG_TSEC_ENET
134 * Clear BD & FR bits for big endian BD's and frame data (aka set
135 * correct eTSEC endianness). This is crucial in ensuring that it does
136 * not report Data Parity Errors in its RX/TX FIFOs when attempting to
139 clrbits_be32(&scfg
->etsecdmamcr
, SCFG_ETSECDMAMCR_LE_BD_FR
);
140 /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
141 out_be32(&scfg
->etsecmcr
, SCFG_ETSECCMCR_GE2_CLK125
);
146 #if defined(CONFIG_DEEP_SLEEP)
147 if (is_warm_boot()) {
156 #ifdef CONFIG_SPL_BUILD
157 void board_init_f(ulong dummy
)
159 void (*second_uboot
)(void);
162 memset(__bss_start
, 0, __bss_end
- __bss_start
);
166 #if defined(CONFIG_DEEP_SLEEP)
168 fsl_dp_disable_console();
171 preloader_console_init();
175 /* Allow OCRAM access permission as R/W */
176 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
177 enable_layerscape_ns_access();
178 enable_layerscape_ns_access();
182 * if it is woken up from deep sleep, then jump to second
183 * stage U-Boot and continue executing without recopying
184 * it from SD since it has already been reserved in memory
187 if (is_warm_boot()) {
188 second_uboot
= (void (*)(void))CONFIG_SYS_TEXT_BASE
;
192 board_init_r(NULL
, 0);
198 #ifndef CONFIG_SYS_FSL_NO_SERDES
201 ls102xa_smmu_stream_id_init();
203 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
204 enable_layerscape_ns_access();
214 #if defined(CONFIG_SPL_BUILD)
215 void spl_board_init(void)
217 ls102xa_smmu_stream_id_init();
221 #ifdef CONFIG_BOARD_LATE_INIT
222 int board_late_init(void)
224 #ifdef CONFIG_CHAIN_OF_TRUST
225 fsl_setenv_chain_of_trust();
232 #if defined(CONFIG_MISC_INIT_R)
233 int misc_init_r(void)
235 #ifdef CONFIG_FSL_DEVICE_DISABLE
236 device_disable(devdis_tbl
, ARRAY_SIZE(devdis_tbl
));
239 #ifdef CONFIG_FSL_CAAM
245 #if defined(CONFIG_DEEP_SLEEP)
246 void board_sleep_prepare(void)
248 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
249 enable_layerscape_ns_access();
254 int ft_board_setup(void *blob
, bd_t
*bd
)
256 ft_cpu_setup(blob
, bd
);
259 ft_pci_setup(blob
, bd
);