board/freescale/ls1043aqds/ls1043aqds.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/fdt.h>
  14 #include <asm/arch/soc.h>
  15 #include <ahci.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <scsi.h>
  19 #include <fm_eth.h>
  20 #include <fsl_csu.h>
  21 #include <fsl_esdhc.h>
  22 #include <fsl_ifc.h>
  23 #include <spl.h>
  24
  25 #include "../common/qixis.h"
  26 #include "ls1043aqds_qixis.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 enum {
  31         MUX_TYPE_GPIO,
  32 };
  33
  34 /* LS1043AQDS serdes mux */
  35 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  36 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  37 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  38 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  39 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  40 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  41 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  42 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  43 #define CFG_UART_MUX_MASK       0x6
  44 #define CFG_UART_MUX_SHIFT      1
  45 #define CFG_LPUART_EN           0x1
  46
  47 int checkboard(void)
  48 {
  49         char buf[64];
  50 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  51         u8 sw;
  52 #endif
  53
  54         puts("Board: LS1043AQDS, boot from ");
  55
  56 #ifdef CONFIG_SD_BOOT
  57         puts("SD\n");
  58 #elif defined(CONFIG_QSPI_BOOT)
  59         puts("QSPI\n");
  60 #else
  61         sw = QIXIS_READ(brdcfg[0]);
  62         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  63
  64         if (sw < 0x8)
  65                 printf("vBank: %d\n", sw);
  66         else if (sw == 0x8)
  67                 puts("PromJet\n");
  68         else if (sw == 0x9)
  69                 puts("NAND\n");
  70         else if (sw == 0x15)
  71                 printf("IFCCard\n");
  72         else
  73                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  74 #endif
  75
  76         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  77                QIXIS_READ(id), QIXIS_READ(arch));
  78
  79         printf("FPGA:  v%d (%s), build %d\n",
  80                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  81                (int)qixis_read_minor());
  82
  83         return 0;
  84 }
  85
  86 bool if_board_diff_clk(void)
  87 {
  88         u8 diff_conf = QIXIS_READ(brdcfg[11]);
  89
  90         return diff_conf & 0x40;
  91 }
  92
  93 unsigned long get_board_sys_clk(void)
  94 {
  95         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  96
  97         switch (sysclk_conf & 0x0f) {
  98         case QIXIS_SYSCLK_64:
  99                 return 64000000;
 100         case QIXIS_SYSCLK_83:
 101                 return 83333333;
 102         case QIXIS_SYSCLK_100:
 103                 return 100000000;
 104         case QIXIS_SYSCLK_125:
 105                 return 125000000;
 106         case QIXIS_SYSCLK_133:
 107                 return 133333333;
 108         case QIXIS_SYSCLK_150:
 109                 return 150000000;
 110         case QIXIS_SYSCLK_160:
 111                 return 160000000;
 112         case QIXIS_SYSCLK_166:
 113                 return 166666666;
 114         }
 115
 116         return 66666666;
 117 }
 118
 119 unsigned long get_board_ddr_clk(void)
 120 {
 121         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 122
 123         if (if_board_diff_clk())
 124                 return get_board_sys_clk();
 125         switch ((ddrclk_conf & 0x30) >> 4) {
 126         case QIXIS_DDRCLK_100:
 127                 return 100000000;
 128         case QIXIS_DDRCLK_125:
 129                 return 125000000;
 130         case QIXIS_DDRCLK_133:
 131                 return 133333333;
 132         }
 133
 134         return 66666666;
 135 }
 136
 137 int select_i2c_ch_pca9547(u8 ch)
 138 {
 139         int ret;
 140
 141         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 142         if (ret) {
 143                 puts("PCA: failed to select proper channel\n");
 144                 return ret;
 145         }
 146
 147         return 0;
 148 }
 149
 150 int dram_init(void)
 151 {
 152         /*
 153          * When resuming from deep sleep, the I2C channel may not be
 154          * in the default channel. So, switch to the default channel
 155          * before accessing DDR SPD.
 156          */
 157         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 158         gd->ram_size = initdram(0);
 159
 160         return 0;
 161 }
 162
 163 int i2c_multiplexer_select_vid_channel(u8 channel)
 164 {
 165         return select_i2c_ch_pca9547(channel);
 166 }
 167
 168 void board_retimer_init(void)
 169 {
 170         u8 reg;
 171
 172         /* Retimer is connected to I2C1_CH7_CH5 */
 173         select_i2c_ch_pca9547(I2C_MUX_CH7);
 174         reg = I2C_MUX_CH5;
 175         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 176
 177         /* Access to Control/Shared register */
 178         reg = 0x0;
 179         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 180
 181         /* Read device revision and ID */
 182         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 183         debug("Retimer version id = 0x%x\n", reg);
 184
 185         /* Enable Broadcast. All writes target all channel register sets */
 186         reg = 0x0c;
 187         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 188
 189         /* Reset Channel Registers */
 190         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 191         reg |= 0x4;
 192         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 193
 194         /* Enable override divider select and Enable Override Output Mux */
 195         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 196         reg |= 0x24;
 197         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 198
 199         /* Select VCO Divider to full rate (000) */
 200         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 201         reg &= 0x8f;
 202         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 203
 204         /* Selects active PFD MUX Input as Re-timed Data (001) */
 205         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 206         reg &= 0x3f;
 207         reg |= 0x20;
 208         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 209
 210         /* Set data rate as 10.3125 Gbps */
 211         reg = 0x0;
 212         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 213         reg = 0xb2;
 214         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 215         reg = 0x90;
 216         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 217         reg = 0xb3;
 218         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 219         reg = 0xcd;
 220         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 221
 222         /* Return the default channel */
 223         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 224 }
 225
 226 int board_early_init_f(void)
 227 {
 228 #ifdef CONFIG_HAS_FSL_XHCI_USB
 229         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 230         u32 usb_pwrfault;
 231 #endif
 232 #ifdef CONFIG_LPUART
 233         u8 uart;
 234 #endif
 235         fsl_lsch2_early_init_f();
 236
 237 #ifdef CONFIG_HAS_FSL_XHCI_USB
 238         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 239         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 240         usb_pwrfault =
 241                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 242                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 243                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 244         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 245 #endif
 246
 247 #ifdef CONFIG_LPUART
 248         /* We use lpuart0 as system console */
 249         uart = QIXIS_READ(brdcfg[14]);
 250         uart &= ~CFG_UART_MUX_MASK;
 251         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 252         QIXIS_WRITE(brdcfg[14], uart);
 253 #endif
 254
 255         return 0;
 256 }
 257
 258 #ifdef CONFIG_FSL_DEEP_SLEEP
 259 /* determine if it is a warm boot */
 260 bool is_warm_boot(void)
 261 {
 262 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 263         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 264
 265         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 266                 return 1;
 267
 268         return 0;
 269 }
 270 #endif
 271
 272 int config_board_mux(int ctrl_type)
 273 {
 274         u8 reg14;
 275
 276         reg14 = QIXIS_READ(brdcfg[14]);
 277
 278         switch (ctrl_type) {
 279         case MUX_TYPE_GPIO:
 280                 reg14 = (reg14 & (~0x30)) | 0x20;
 281                 break;
 282         default:
 283                 puts("Unsupported mux interface type\n");
 284                 return -1;
 285         }
 286
 287         QIXIS_WRITE(brdcfg[14], reg14);
 288
 289         return 0;
 290 }
 291
 292 int config_serdes_mux(void)
 293 {
 294         return 0;
 295 }
 296
 297
 298 #ifdef CONFIG_MISC_INIT_R
 299 int misc_init_r(void)
 300 {
 301         if (hwconfig("gpio"))
 302                 config_board_mux(MUX_TYPE_GPIO);
 303
 304         return 0;
 305 }
 306 #endif
 307
 308 int board_init(void)
 309 {
 310         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
 311                                    CONFIG_SYS_CCI400_ADDR;
 312
 313         /* Set CCI-400 control override register to enable barrier
 314          * transaction */
 315         out_le32(&cci->ctrl_ord,
 316                  CCI400_CTRLORD_EN_BARRIER);
 317
 318         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 319         board_retimer_init();
 320
 321 #ifdef CONFIG_SYS_FSL_SERDES
 322         config_serdes_mux();
 323 #endif
 324
 325 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 326         enable_layerscape_ns_access();
 327 #endif
 328
 329 #ifdef CONFIG_ENV_IS_NOWHERE
 330         gd->env_addr = (ulong)&default_environment[0];
 331 #endif
 332         return 0;
 333 }
 334
 335 #ifdef CONFIG_OF_BOARD_SETUP
 336 int ft_board_setup(void *blob, bd_t *bd)
 337 {
 338         u64 base[CONFIG_NR_DRAM_BANKS];
 339         u64 size[CONFIG_NR_DRAM_BANKS];
 340
 341         /* fixup DT for the two DDR banks */
 342         base[0] = gd->bd->bi_dram[0].start;
 343         size[0] = gd->bd->bi_dram[0].size;
 344         base[1] = gd->bd->bi_dram[1].start;
 345         size[1] = gd->bd->bi_dram[1].size;
 346
 347         fdt_fixup_memory_banks(blob, base, size, 2);
 348         ft_cpu_setup(blob, bd);
 349
 350 #ifdef CONFIG_SYS_DPAA_FMAN
 351         fdt_fixup_fman_ethernet(blob);
 352         fdt_fixup_board_enet(blob);
 353 #endif
 354         return 0;
 355 }
 356 #endif
 357
 358 u8 flash_read8(void *addr)
 359 {
 360         return __raw_readb(addr + 1);
 361 }
 362
 363 void flash_write16(u16 val, void *addr)
 364 {
 365         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 366
 367         __raw_writew(shftval, addr);
 368 }
 369
 370 u16 flash_read16(void *addr)
 371 {
 372         u16 val = __raw_readw(addr);
 373
 374         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 375 }