board/freescale/ls1043aqds/ls1043aqds.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/fdt.h>
  14 #include <asm/arch/soc.h>
  15 #include <ahci.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <scsi.h>
  19 #include <fm_eth.h>
  20 #include <fsl_esdhc.h>
  21 #include <fsl_ifc.h>
  22 #include <spl.h>
  23
  24 #include "../common/qixis.h"
  25 #include "ls1043aqds_qixis.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 enum {
  30         MUX_TYPE_GPIO,
  31 };
  32
  33 /* LS1043AQDS serdes mux */
  34 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  35 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  36 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  37 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  38 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  39 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  40 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  41 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  42 #define CFG_UART_MUX_MASK       0x6
  43 #define CFG_UART_MUX_SHIFT      1
  44 #define CFG_LPUART_EN           0x1
  45
  46 int checkboard(void)
  47 {
  48         char buf[64];
  49 #ifndef CONFIG_SD_BOOT
  50         u8 sw;
  51 #endif
  52
  53         puts("Board: LS1043AQDS, boot from ");
  54
  55 #ifdef CONFIG_SD_BOOT
  56         puts("SD\n");
  57 #else
  58         sw = QIXIS_READ(brdcfg[0]);
  59         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  60
  61         if (sw < 0x8)
  62                 printf("vBank: %d\n", sw);
  63         else if (sw == 0x8)
  64                 puts("PromJet\n");
  65         else if (sw == 0x9)
  66                 puts("NAND\n");
  67         else if (sw == 0xF)
  68                 printf("QSPI\n");
  69         else
  70                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  71 #endif
  72
  73         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  74                QIXIS_READ(id), QIXIS_READ(arch));
  75
  76         printf("FPGA:  v%d (%s), build %d\n",
  77                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  78                (int)qixis_read_minor());
  79
  80         return 0;
  81 }
  82
  83 bool if_board_diff_clk(void)
  84 {
  85         u8 diff_conf = QIXIS_READ(brdcfg[11]);
  86
  87         return diff_conf & 0x40;
  88 }
  89
  90 unsigned long get_board_sys_clk(void)
  91 {
  92         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  93
  94         switch (sysclk_conf & 0x0f) {
  95         case QIXIS_SYSCLK_64:
  96                 return 64000000;
  97         case QIXIS_SYSCLK_83:
  98                 return 83333333;
  99         case QIXIS_SYSCLK_100:
 100                 return 100000000;
 101         case QIXIS_SYSCLK_125:
 102                 return 125000000;
 103         case QIXIS_SYSCLK_133:
 104                 return 133333333;
 105         case QIXIS_SYSCLK_150:
 106                 return 150000000;
 107         case QIXIS_SYSCLK_160:
 108                 return 160000000;
 109         case QIXIS_SYSCLK_166:
 110                 return 166666666;
 111         }
 112
 113         return 66666666;
 114 }
 115
 116 unsigned long get_board_ddr_clk(void)
 117 {
 118         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 119
 120         if (if_board_diff_clk())
 121                 return get_board_sys_clk();
 122         switch ((ddrclk_conf & 0x30) >> 4) {
 123         case QIXIS_DDRCLK_100:
 124                 return 100000000;
 125         case QIXIS_DDRCLK_125:
 126                 return 125000000;
 127         case QIXIS_DDRCLK_133:
 128                 return 133333333;
 129         }
 130
 131         return 66666666;
 132 }
 133
 134 int select_i2c_ch_pca9547(u8 ch)
 135 {
 136         int ret;
 137
 138         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 139         if (ret) {
 140                 puts("PCA: failed to select proper channel\n");
 141                 return ret;
 142         }
 143
 144         return 0;
 145 }
 146
 147 int dram_init(void)
 148 {
 149         /*
 150          * When resuming from deep sleep, the I2C channel may not be
 151          * in the default channel. So, switch to the default channel
 152          * before accessing DDR SPD.
 153          */
 154         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 155         gd->ram_size = initdram(0);
 156
 157         return 0;
 158 }
 159
 160 int i2c_multiplexer_select_vid_channel(u8 channel)
 161 {
 162         return select_i2c_ch_pca9547(channel);
 163 }
 164
 165 void board_retimer_init(void)
 166 {
 167         u8 reg;
 168
 169         /* Retimer is connected to I2C1_CH7_CH5 */
 170         select_i2c_ch_pca9547(I2C_MUX_CH7);
 171         reg = I2C_MUX_CH5;
 172         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 173
 174         /* Access to Control/Shared register */
 175         reg = 0x0;
 176         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 177
 178         /* Read device revision and ID */
 179         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 180         debug("Retimer version id = 0x%x\n", reg);
 181
 182         /* Enable Broadcast. All writes target all channel register sets */
 183         reg = 0x0c;
 184         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 185
 186         /* Reset Channel Registers */
 187         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 188         reg |= 0x4;
 189         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 190
 191         /* Enable override divider select and Enable Override Output Mux */
 192         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 193         reg |= 0x24;
 194         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 195
 196         /* Select VCO Divider to full rate (000) */
 197         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 198         reg &= 0x8f;
 199         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 200
 201         /* Selects active PFD MUX Input as Re-timed Data (001) */
 202         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 203         reg &= 0x3f;
 204         reg |= 0x20;
 205         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 206
 207         /* Set data rate as 10.3125 Gbps */
 208         reg = 0x0;
 209         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 210         reg = 0xb2;
 211         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 212         reg = 0x90;
 213         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 214         reg = 0xb3;
 215         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 216         reg = 0xcd;
 217         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 218
 219         /* Return the default channel */
 220         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 221 }
 222
 223 int board_early_init_f(void)
 224 {
 225 #ifdef CONFIG_HAS_FSL_XHCI_USB
 226         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 227         u32 usb_pwrfault;
 228 #endif
 229 #ifdef CONFIG_LPUART
 230         u8 uart;
 231 #endif
 232
 233 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 234         i2c_early_init_f();
 235 #endif
 236         fsl_lsch2_early_init_f();
 237
 238 #ifdef CONFIG_HAS_FSL_XHCI_USB
 239         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 240         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 241         usb_pwrfault =
 242                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 243                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 244                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 245         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 246 #endif
 247
 248 #ifdef CONFIG_LPUART
 249         /* We use lpuart0 as system console */
 250         uart = QIXIS_READ(brdcfg[14]);
 251         uart &= ~CFG_UART_MUX_MASK;
 252         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 253         QIXIS_WRITE(brdcfg[14], uart);
 254 #endif
 255
 256         return 0;
 257 }
 258
 259 #ifdef CONFIG_FSL_DEEP_SLEEP
 260 /* determine if it is a warm boot */
 261 bool is_warm_boot(void)
 262 {
 263 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 264         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 265
 266         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 267                 return 1;
 268
 269         return 0;
 270 }
 271 #endif
 272
 273 int config_board_mux(int ctrl_type)
 274 {
 275         u8 reg14;
 276
 277         reg14 = QIXIS_READ(brdcfg[14]);
 278
 279         switch (ctrl_type) {
 280         case MUX_TYPE_GPIO:
 281                 reg14 = (reg14 & (~0x30)) | 0x20;
 282                 break;
 283         default:
 284                 puts("Unsupported mux interface type\n");
 285                 return -1;
 286         }
 287
 288         QIXIS_WRITE(brdcfg[14], reg14);
 289
 290         return 0;
 291 }
 292
 293 int config_serdes_mux(void)
 294 {
 295         return 0;
 296 }
 297
 298
 299 #ifdef CONFIG_MISC_INIT_R
 300 int misc_init_r(void)
 301 {
 302         if (hwconfig("gpio"))
 303                 config_board_mux(MUX_TYPE_GPIO);
 304
 305         return 0;
 306 }
 307 #endif
 308
 309 int board_init(void)
 310 {
 311 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 312         erratum_a010315();
 313 #endif
 314
 315         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 316         board_retimer_init();
 317
 318 #ifdef CONFIG_SYS_FSL_SERDES
 319         config_serdes_mux();
 320 #endif
 321
 322         return 0;
 323 }
 324
 325 #ifdef CONFIG_OF_BOARD_SETUP
 326 int ft_board_setup(void *blob, bd_t *bd)
 327 {
 328         u64 base[CONFIG_NR_DRAM_BANKS];
 329         u64 size[CONFIG_NR_DRAM_BANKS];
 330         u8 reg;
 331
 332         /* fixup DT for the two DDR banks */
 333         base[0] = gd->bd->bi_dram[0].start;
 334         size[0] = gd->bd->bi_dram[0].size;
 335         base[1] = gd->bd->bi_dram[1].start;
 336         size[1] = gd->bd->bi_dram[1].size;
 337
 338         fdt_fixup_memory_banks(blob, base, size, 2);
 339         ft_cpu_setup(blob, bd);
 340
 341 #ifdef CONFIG_SYS_DPAA_FMAN
 342         fdt_fixup_fman_ethernet(blob);
 343         fdt_fixup_board_enet(blob);
 344 #endif
 345
 346         reg = QIXIS_READ(brdcfg[0]);
 347         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 348
 349         /* Disable IFC if QSPI is enabled */
 350         if (reg == 0xF)
 351                 do_fixup_by_compat(blob, "fsl,ifc",
 352                                    "status", "disabled", 8 + 1, 1);
 353
 354         return 0;
 355 }
 356 #endif
 357
 358 u8 flash_read8(void *addr)
 359 {
 360         return __raw_readb(addr + 1);
 361 }
 362
 363 void flash_write16(u16 val, void *addr)
 364 {
 365         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 366
 367         __raw_writew(shftval, addr);
 368 }
 369
 370 u16 flash_read16(void *addr)
 371 {
 372         u16 val = __raw_readw(addr);
 373
 374         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 375 }