4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
17 #include <fsl-mc/ldpaa_wriop.h>
19 #include "../common/qixis.h"
21 #include "ls1088a_qixis.h"
23 #define MC_BOOT_ENV_VAR "mcinitcmd"
25 #ifdef CONFIG_FSL_MC_ENET
29 /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D,
31 * Bank 2 -> Lanes A,B, C, D,
34 /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
35 * means that the mapping must be determined dynamically, or that the lane
36 * maps to something other than a board slot.
39 static u8 lane_to_slot_fsm1
[] = {
40 0, 0, 0, 0, 0, 0, 0, 0
43 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
47 static int xqsgii_riser_phy_addr
[] = {
48 XQSGMII_CARD_PHY1_PORT0_ADDR
,
49 XQSGMII_CARD_PHY2_PORT0_ADDR
,
50 XQSGMII_CARD_PHY3_PORT0_ADDR
,
51 XQSGMII_CARD_PHY4_PORT0_ADDR
,
52 XQSGMII_CARD_PHY3_PORT2_ADDR
,
53 XQSGMII_CARD_PHY1_PORT2_ADDR
,
54 XQSGMII_CARD_PHY4_PORT2_ADDR
,
55 XQSGMII_CARD_PHY2_PORT2_ADDR
,
58 static int sgmii_riser_phy_addr
[] = {
59 SGMII_CARD_PORT1_PHY_ADDR
,
60 SGMII_CARD_PORT2_PHY_ADDR
,
61 SGMII_CARD_PORT3_PHY_ADDR
,
62 SGMII_CARD_PORT4_PHY_ADDR
,
65 /* Slot2 does not have EMI connections */
71 static const char * const mdio_names
[] = {
75 DEFAULT_WRIOP_MDIO2_NAME
,
78 struct ls1088a_qds_mdio
{
80 struct mii_dev
*realbus
;
83 static void sgmii_configure_repeater(int dpmac
)
89 const char *dev
= "LS1088A_QDS_MDIO2";
90 int i2c_addr
[] = {0x58, 0x59, 0x5a, 0x5b};
94 uint8_t ch_a_eq
[] = {0x1, 0x2, 0x3, 0x7};
95 uint8_t ch_a_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
96 uint8_t ch_b_eq
[] = {0x1, 0x2, 0x3, 0x7};
97 uint8_t ch_b_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
99 /* Set I2c to Slot 1 */
100 i2c_write(0x77, 0, 0, &a
, 1);
104 i2c_phy_addr
= i2c_addr
[1];
108 i2c_phy_addr
= i2c_addr
[0];
112 i2c_phy_addr
= i2c_addr
[3];
116 i2c_phy_addr
= i2c_addr
[2];
121 /* Check the PHY status */
122 ret
= miiphy_set_current_dev(dev
);
126 bus
= mdio_get_current_dev();
127 debug("Reading from bus %s\n", bus
->name
);
129 ret
= miiphy_write(dev
, phy_addr
, 0x1f, 3);
134 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
140 if ((value
& 0xfff) == 0x401) {
141 miiphy_write(dev
, phy_addr
, 0x1f, 0);
142 printf("DPMAC %d:PHY is ..... Configured\n", dpmac
);
146 for (i
= 0; i
< 4; i
++) {
147 for (j
= 0; j
< 4; j
++) {
149 i2c_write(i2c_phy_addr
, 6, 1, &a
, 1);
151 i2c_write(i2c_phy_addr
, 4, 1, &a
, 1);
153 i2c_write(i2c_phy_addr
, 8, 1, &a
, 1);
155 i2c_write(i2c_phy_addr
, 0xf, 1,
157 i2c_write(i2c_phy_addr
, 0x11, 1,
160 i2c_write(i2c_phy_addr
, 0x16, 1,
162 i2c_write(i2c_phy_addr
, 0x18, 1,
166 i2c_write(i2c_phy_addr
, 0x23, 1, &a
, 1);
168 i2c_write(i2c_phy_addr
, 0x2d, 1, &a
, 1);
170 i2c_write(i2c_phy_addr
, 4, 1, &a
, 1);
172 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
177 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
181 if ((value
& 0xfff) == 0x401) {
182 printf("DPMAC %d :PHY is configured ",
184 printf("after setting repeater 0x%x\n",
189 printf("DPMAC %d :PHY is failed to ",
191 printf("configure the repeater 0x%x\n", value
);
195 miiphy_write(dev
, phy_addr
, 0x1f, 0);
198 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac
);
202 static void qsgmii_configure_repeater(int dpmac
)
206 int i2c_phy_addr
= 0;
208 int i2c_addr
[] = {0x58, 0x59, 0x5a, 0x5b};
210 uint8_t ch_a_eq
[] = {0x1, 0x2, 0x3, 0x7};
211 uint8_t ch_a_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
212 uint8_t ch_b_eq
[] = {0x1, 0x2, 0x3, 0x7};
213 uint8_t ch_b_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
215 const char *dev
= mdio_names
[EMI1_SLOT1
];
217 unsigned short value
;
219 /* Set I2c to Slot 1 */
220 i2c_write(0x77, 0, 0, &a
, 1);
227 i2c_phy_addr
= i2c_addr
[2];
235 i2c_phy_addr
= i2c_addr
[3];
240 /* Check the PHY status */
241 ret
= miiphy_set_current_dev(dev
);
242 ret
= miiphy_write(dev
, phy_addr
, 0x1f, 3);
244 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
246 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
248 if ((value
& 0xf) == 0xf) {
249 miiphy_write(dev
, phy_addr
, 0x1f, 0);
250 printf("DPMAC %d :PHY is ..... Configured\n", dpmac
);
254 for (i
= 0; i
< 4; i
++) {
255 for (j
= 0; j
< 4; j
++) {
257 i2c_write(i2c_phy_addr
, 6, 1, &a
, 1);
259 i2c_write(i2c_phy_addr
, 4, 1, &a
, 1);
261 i2c_write(i2c_phy_addr
, 8, 1, &a
, 1);
263 i2c_write(i2c_phy_addr
, 0xf, 1, &ch_a_eq
[i
], 1);
264 i2c_write(i2c_phy_addr
, 0x11, 1, &ch_a_ctl2
[j
], 1);
266 i2c_write(i2c_phy_addr
, 0x16, 1, &ch_b_eq
[i
], 1);
267 i2c_write(i2c_phy_addr
, 0x18, 1, &ch_b_ctl2
[j
], 1);
270 i2c_write(i2c_phy_addr
, 0x23, 1, &a
, 1);
272 i2c_write(i2c_phy_addr
, 0x2d, 1, &a
, 1);
274 i2c_write(i2c_phy_addr
, 4, 1, &a
, 1);
276 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
280 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
284 if ((value
& 0xf) == 0xf) {
285 miiphy_write(dev
, phy_addr
, 0x1f, 0);
286 printf("DPMAC %d :PHY is ..... Configured\n",
293 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac
);
297 static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval
)
299 return mdio_names
[muxval
];
302 struct mii_dev
*mii_dev_for_muxval(u8 muxval
)
305 const char *name
= ls1088a_qds_mdio_name_for_muxval(muxval
);
308 printf("No bus for muxval %x\n", muxval
);
312 bus
= miiphy_get_dev_by_name(name
);
315 printf("No bus by name %s\n", name
);
322 static void ls1088a_qds_enable_SFP_TX(u8 muxval
)
326 brdcfg9
= QIXIS_READ(brdcfg
[9]);
327 brdcfg9
&= ~BRDCFG9_SFPTX_MASK
;
328 brdcfg9
|= (muxval
<< BRDCFG9_SFPTX_SHIFT
);
329 QIXIS_WRITE(brdcfg
[9], brdcfg9
);
332 static void ls1088a_qds_mux_mdio(u8 muxval
)
337 brdcfg4
= QIXIS_READ(brdcfg
[4]);
338 brdcfg4
&= ~BRDCFG4_EMISEL_MASK
;
339 brdcfg4
|= (muxval
<< BRDCFG4_EMISEL_SHIFT
);
340 QIXIS_WRITE(brdcfg
[4], brdcfg4
);
344 static int ls1088a_qds_mdio_read(struct mii_dev
*bus
, int addr
,
345 int devad
, int regnum
)
347 struct ls1088a_qds_mdio
*priv
= bus
->priv
;
349 ls1088a_qds_mux_mdio(priv
->muxval
);
351 return priv
->realbus
->read(priv
->realbus
, addr
, devad
, regnum
);
354 static int ls1088a_qds_mdio_write(struct mii_dev
*bus
, int addr
, int devad
,
355 int regnum
, u16 value
)
357 struct ls1088a_qds_mdio
*priv
= bus
->priv
;
359 ls1088a_qds_mux_mdio(priv
->muxval
);
361 return priv
->realbus
->write(priv
->realbus
, addr
, devad
, regnum
, value
);
364 static int ls1088a_qds_mdio_reset(struct mii_dev
*bus
)
366 struct ls1088a_qds_mdio
*priv
= bus
->priv
;
368 return priv
->realbus
->reset(priv
->realbus
);
371 static int ls1088a_qds_mdio_init(char *realbusname
, u8 muxval
)
373 struct ls1088a_qds_mdio
*pmdio
;
374 struct mii_dev
*bus
= mdio_alloc();
377 printf("Failed to allocate ls1088a_qds MDIO bus\n");
381 pmdio
= malloc(sizeof(*pmdio
));
383 printf("Failed to allocate ls1088a_qds private data\n");
388 bus
->read
= ls1088a_qds_mdio_read
;
389 bus
->write
= ls1088a_qds_mdio_write
;
390 bus
->reset
= ls1088a_qds_mdio_reset
;
391 sprintf(bus
->name
, ls1088a_qds_mdio_name_for_muxval(muxval
));
393 pmdio
->realbus
= miiphy_get_dev_by_name(realbusname
);
395 if (!pmdio
->realbus
) {
396 printf("No bus with name %s\n", realbusname
);
402 pmdio
->muxval
= muxval
;
405 return mdio_register(bus
);
409 * Initialize the dpmac_info array.
412 static void initialize_dpmac_to_slot(void)
414 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
415 u32 serdes1_prtcl
, cfg
;
417 cfg
= in_le32(&gur
->rcwsr
[FSL_CHASSIS3_SRDS1_REGSR
- 1]) &
418 FSL_CHASSIS3_SRDS1_PRTCL_MASK
;
419 cfg
>>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
;
420 serdes1_prtcl
= serdes_get_number(FSL_SRDS_1
, cfg
);
422 switch (serdes1_prtcl
) {
424 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
426 lane_to_slot_fsm1
[0] = EMI1_SLOT1
- 1;
427 lane_to_slot_fsm1
[1] = EMI1_SLOT1
- 1;
428 lane_to_slot_fsm1
[2] = EMI1_SLOT1
- 1;
429 lane_to_slot_fsm1
[3] = EMI1_SLOT1
- 1;
433 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
435 lane_to_slot_fsm1
[0] = EMI1_SLOT1
- 1;
436 lane_to_slot_fsm1
[1] = EMI1_SLOT1
- 1;
437 lane_to_slot_fsm1
[2] = EMI_NONE
;
438 lane_to_slot_fsm1
[3] = EMI_NONE
;
441 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
443 lane_to_slot_fsm1
[0] = EMI1_SLOT1
- 1;
444 lane_to_slot_fsm1
[1] = EMI1_SLOT1
- 1;
445 lane_to_slot_fsm1
[2] = EMI1_SLOT1
- 1;
446 lane_to_slot_fsm1
[3] = EMI_NONE
;
449 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
451 lane_to_slot_fsm1
[0] = EMI1_SLOT1
- 1;
452 lane_to_slot_fsm1
[1] = EMI_NONE
;
453 lane_to_slot_fsm1
[2] = EMI1_SLOT1
- 1;
454 lane_to_slot_fsm1
[3] = EMI1_SLOT1
- 1;
458 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
459 __func__
, serdes1_prtcl
);
464 void ls1088a_handle_phy_interface_sgmii(int dpmac_id
)
467 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
468 u32 serdes1_prtcl
, cfg
;
470 cfg
= in_le32(&gur
->rcwsr
[FSL_CHASSIS3_SRDS1_REGSR
- 1]) &
471 FSL_CHASSIS3_SRDS1_PRTCL_MASK
;
472 cfg
>>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
;
473 serdes1_prtcl
= serdes_get_number(FSL_SRDS_1
, cfg
);
476 char *env_hwconfig
= env_get("hwconfig");
478 if (hwconfig_f("xqsgmii", env_hwconfig
))
479 riser_phy_addr
= &xqsgii_riser_phy_addr
[0];
481 riser_phy_addr
= &sgmii_riser_phy_addr
[0];
483 switch (serdes1_prtcl
) {
490 wriop_set_phy_address(dpmac_id
, riser_phy_addr
[1]);
493 wriop_set_phy_address(dpmac_id
, riser_phy_addr
[0]);
496 wriop_set_phy_address(dpmac_id
, riser_phy_addr
[3]);
499 wriop_set_phy_address(dpmac_id
, riser_phy_addr
[2]);
502 printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id
);
507 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
508 __func__
, serdes1_prtcl
);
511 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT1
;
512 bus
= mii_dev_for_muxval(EMI1_SLOT1
);
513 wriop_set_mdio(dpmac_id
, bus
);
516 void ls1088a_handle_phy_interface_qsgmii(int dpmac_id
)
519 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
520 u32 serdes1_prtcl
, cfg
;
522 cfg
= in_le32(&gur
->rcwsr
[FSL_CHASSIS3_SRDS1_REGSR
- 1]) &
523 FSL_CHASSIS3_SRDS1_PRTCL_MASK
;
524 cfg
>>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
;
525 serdes1_prtcl
= serdes_get_number(FSL_SRDS_1
, cfg
);
527 switch (serdes1_prtcl
) {
535 wriop_set_phy_address(dpmac_id
, dpmac_id
+ 9);
541 wriop_set_phy_address(dpmac_id
, dpmac_id
+ 1);
545 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT1
;
546 bus
= mii_dev_for_muxval(EMI1_SLOT1
);
547 wriop_set_mdio(dpmac_id
, bus
);
550 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
556 void ls1088a_handle_phy_interface_xsgmii(int i
)
558 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
559 u32 serdes1_prtcl
, cfg
;
561 cfg
= in_le32(&gur
->rcwsr
[FSL_CHASSIS3_SRDS1_REGSR
- 1]) &
562 FSL_CHASSIS3_SRDS1_PRTCL_MASK
;
563 cfg
>>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
;
564 serdes1_prtcl
= serdes_get_number(FSL_SRDS_1
, cfg
);
566 switch (serdes1_prtcl
) {
570 wriop_set_phy_address(i
, i
+ 26);
571 ls1088a_qds_enable_SFP_TX(SFP_TX
);
574 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
581 int board_eth_init(bd_t
*bis
)
584 char *mc_boot_env_var
;
585 #ifdef CONFIG_FSL_MC_ENET
586 struct memac_mdio_info
*memac_mdio0_info
;
587 char *env_hwconfig
= env_get("hwconfig");
589 initialize_dpmac_to_slot();
591 memac_mdio0_info
= (struct memac_mdio_info
*)malloc(
592 sizeof(struct memac_mdio_info
));
593 memac_mdio0_info
->regs
=
594 (struct memac_mdio_controller
*)
595 CONFIG_SYS_FSL_WRIOP1_MDIO1
;
596 memac_mdio0_info
->name
= DEFAULT_WRIOP_MDIO1_NAME
;
598 /* Register the real MDIO1 bus */
599 fm_memac_mdio_init(bis
, memac_mdio0_info
);
601 /* Register the muxing front-ends to the MDIO buses */
602 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_RGMII1
);
603 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_RGMII2
);
604 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_SLOT1
);
606 for (i
= WRIOP1_DPMAC1
; i
< NUM_WRIOP_PORTS
; i
++) {
607 switch (wriop_get_enet_if(i
)) {
608 case PHY_INTERFACE_MODE_QSGMII
:
609 ls1088a_handle_phy_interface_qsgmii(i
);
611 case PHY_INTERFACE_MODE_SGMII
:
612 ls1088a_handle_phy_interface_sgmii(i
);
614 case PHY_INTERFACE_MODE_XGMII
:
615 ls1088a_handle_phy_interface_xsgmii(i
);
625 mc_boot_env_var
= env_get(MC_BOOT_ENV_VAR
);
627 run_command_list(mc_boot_env_var
, -1, 0);
628 error
= cpu_eth_init(bis
);
630 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
631 for (i
= WRIOP1_DPMAC1
; i
< NUM_WRIOP_PORTS
; i
++) {
632 switch (wriop_get_enet_if(i
)) {
633 case PHY_INTERFACE_MODE_QSGMII
:
634 qsgmii_configure_repeater(i
);
636 case PHY_INTERFACE_MODE_SGMII
:
637 sgmii_configure_repeater(i
);
648 error
= pci_eth_init(bis
);