board/freescale/ls1088a/ls1088a.c

   1 /*
   2  * Copyright 2017 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <malloc.h>
   9 #include <errno.h>
  10 #include <netdev.h>
  11 #include <fsl_ifc.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_sec.h>
  14 #include <asm/io.h>
  15 #include <fdt_support.h>
  16 #include <libfdt.h>
  17 #include <fsl-mc/fsl_mc.h>
  18 #include <environment.h>
  19 #include <asm/arch-fsl-layerscape/soc.h>
  20 #include <asm/arch/ppa.h>
  21 #include <hwconfig.h>
  22
  23 #include "../common/qixis.h"
  24 #include "ls1088a_qixis.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 unsigned long long get_qixis_addr(void)
  29 {
  30         unsigned long long addr;
  31
  32         if (gd->flags & GD_FLG_RELOC)
  33                 addr = QIXIS_BASE_PHYS;
  34         else
  35                 addr = QIXIS_BASE_PHYS_EARLY;
  36
  37         /*
  38          * IFC address under 256MB is mapped to 0x30000000, any address above
  39          * is mapped to 0x5_10000000 up to 4GB.
  40          */
  41         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  42
  43         return addr;
  44 }
  45
  46 int checkboard(void)
  47 {
  48         char buf[64];
  49         u8 sw;
  50         static const char *const freq[] = {"100", "125", "156.25",
  51                                             "100 separate SSCG"};
  52         int clock;
  53
  54 #ifdef CONFIG_TARGET_LS1088AQDS
  55         printf("Board: LS1088A-QDS, ");
  56 #else
  57         printf("Board: LS1088A-RDB, ");
  58 #endif
  59
  60         sw = QIXIS_READ(arch);
  61         printf("Board Arch: V%d, ", sw >> 4);
  62
  63 #ifdef CONFIG_TARGET_LS1088AQDS
  64         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  65 #else
  66         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  67 #endif
  68
  69         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  70
  71         sw = QIXIS_READ(brdcfg[0]);
  72         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  73
  74 #ifdef CONFIG_SD_BOOT
  75         puts("SD card\n");
  76 #endif
  77         switch (sw) {
  78 #ifdef CONFIG_TARGET_LS1088AQDS
  79         case 0:
  80         case 1:
  81         case 2:
  82         case 3:
  83         case 4:
  84         case 5:
  85         case 6:
  86         case 7:
  87                 printf("vBank: %d\n", sw);
  88                 break;
  89         case 8:
  90                 puts("PromJet\n");
  91                 break;
  92         case 15:
  93                 puts("IFCCard\n");
  94                 break;
  95         case 14:
  96 #else
  97         case 0:
  98 #endif
  99                 puts("QSPI:");
 100                 sw = QIXIS_READ(brdcfg[0]);
 101                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 102                 if (sw == 0 || sw == 4)
 103                         puts("0\n");
 104                 else if (sw == 1)
 105                         puts("1\n");
 106                 else
 107                         puts("EMU\n");
 108                 break;
 109
 110         default:
 111                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 112                 break;
 113         }
 114
 115 #ifdef CONFIG_TARGET_LS1088AQDS
 116         printf("FPGA: v%d (%s), build %d",
 117                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 118                (int)qixis_read_minor());
 119         /* the timestamp string contains "\n" at the end */
 120         printf(" on %s", qixis_read_time(buf));
 121 #else
 122         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 123 #endif
 124
 125         /*
 126          * Display the actual SERDES reference clocks as configured by the
 127          * dip switches on the board.  Note that the SWx registers could
 128          * technically be set to force the reference clocks to match the
 129          * values that the SERDES expects (or vice versa).  For now, however,
 130          * we just display both values and hope the user notices when they
 131          * don't match.
 132          */
 133         puts("SERDES1 Reference : ");
 134         sw = QIXIS_READ(brdcfg[2]);
 135         clock = (sw >> 6) & 3;
 136         printf("Clock1 = %sMHz ", freq[clock]);
 137         clock = (sw >> 4) & 3;
 138         printf("Clock2 = %sMHz", freq[clock]);
 139
 140         puts("\nSERDES2 Reference : ");
 141         clock = (sw >> 2) & 3;
 142         printf("Clock1 = %sMHz ", freq[clock]);
 143         clock = (sw >> 0) & 3;
 144         printf("Clock2 = %sMHz\n", freq[clock]);
 145
 146         return 0;
 147 }
 148
 149 bool if_board_diff_clk(void)
 150 {
 151 #ifdef CONFIG_TARGET_LS1088AQDS
 152         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 153         return diff_conf & 0x40;
 154 #else
 155         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 156         return diff_conf & 0x80;
 157 #endif
 158 }
 159
 160 unsigned long get_board_sys_clk(void)
 161 {
 162         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 163
 164         switch (sysclk_conf & 0x0f) {
 165         case QIXIS_SYSCLK_83:
 166                 return 83333333;
 167         case QIXIS_SYSCLK_100:
 168                 return 100000000;
 169         case QIXIS_SYSCLK_125:
 170                 return 125000000;
 171         case QIXIS_SYSCLK_133:
 172                 return 133333333;
 173         case QIXIS_SYSCLK_150:
 174                 return 150000000;
 175         case QIXIS_SYSCLK_160:
 176                 return 160000000;
 177         case QIXIS_SYSCLK_166:
 178                 return 166666666;
 179         }
 180
 181         return 66666666;
 182 }
 183
 184 unsigned long get_board_ddr_clk(void)
 185 {
 186         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 187
 188         if (if_board_diff_clk())
 189                 return get_board_sys_clk();
 190         switch ((ddrclk_conf & 0x30) >> 4) {
 191         case QIXIS_DDRCLK_100:
 192                 return 100000000;
 193         case QIXIS_DDRCLK_125:
 194                 return 125000000;
 195         case QIXIS_DDRCLK_133:
 196                 return 133333333;
 197         }
 198
 199         return 66666666;
 200 }
 201
 202 int select_i2c_ch_pca9547(u8 ch)
 203 {
 204         int ret;
 205
 206         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 207         if (ret) {
 208                 puts("PCA: failed to select proper channel\n");
 209                 return ret;
 210         }
 211
 212         return 0;
 213 }
 214
 215 void board_retimer_init(void)
 216 {
 217         u8 reg;
 218
 219         /* Retimer is connected to I2C1_CH5 */
 220         select_i2c_ch_pca9547(I2C_MUX_CH5);
 221
 222         /* Access to Control/Shared register */
 223         reg = 0x0;
 224         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 225
 226         /* Read device revision and ID */
 227         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 228         debug("Retimer version id = 0x%x\n", reg);
 229
 230         /* Enable Broadcast. All writes target all channel register sets */
 231         reg = 0x0c;
 232         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 233
 234         /* Reset Channel Registers */
 235         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 236         reg |= 0x4;
 237         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 238
 239         /* Set data rate as 10.3125 Gbps */
 240         reg = 0x90;
 241         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 242         reg = 0xb3;
 243         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 244         reg = 0x90;
 245         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 246         reg = 0xb3;
 247         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 248         reg = 0xcd;
 249         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 250
 251         /* Select VCO Divider to full rate (000) */
 252         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 253         reg &= 0x0f;
 254         reg |= 0x70;
 255         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 256
 257 #ifdef  CONFIG_TARGET_LS1088AQDS
 258         /* Retimer is connected to I2C1_CH5 */
 259         select_i2c_ch_pca9547(I2C_MUX_CH5);
 260
 261         /* Access to Control/Shared register */
 262         reg = 0x0;
 263         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 264
 265         /* Read device revision and ID */
 266         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 267         debug("Retimer version id = 0x%x\n", reg);
 268
 269         /* Enable Broadcast. All writes target all channel register sets */
 270         reg = 0x0c;
 271         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 272
 273         /* Reset Channel Registers */
 274         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 275         reg |= 0x4;
 276         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 277
 278         /* Set data rate as 10.3125 Gbps */
 279         reg = 0x90;
 280         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 281         reg = 0xb3;
 282         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 283         reg = 0x90;
 284         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 285         reg = 0xb3;
 286         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 287         reg = 0xcd;
 288         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 289
 290         /* Select VCO Divider to full rate (000) */
 291         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 292         reg &= 0x0f;
 293         reg |= 0x70;
 294         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 295 #endif
 296         /*return the default channel*/
 297         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 298 }
 299
 300 #ifdef CONFIG_MISC_INIT_R
 301 int misc_init_r(void)
 302 {
 303 #ifdef CONFIG_TARGET_LS1088ARDB
 304         u8 brdcfg5;
 305
 306         if (hwconfig("esdhc-force-sd")) {
 307                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 308                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 309                 brdcfg5 |= BRDCFG5_FORCE_SD;
 310                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 311         }
 312 #endif
 313         return 0;
 314 }
 315 #endif
 316
 317 int board_init(void)
 318 {
 319         init_final_memctl_regs();
 320 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 321         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 322 #endif
 323
 324         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 325         board_retimer_init();
 326
 327 #ifdef CONFIG_ENV_IS_NOWHERE
 328         gd->env_addr = (ulong)&default_environment[0];
 329 #endif
 330
 331 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 332         /* invert AQR105 IRQ pins polarity */
 333         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 334 #endif
 335
 336 #ifdef CONFIG_FSL_CAAM
 337         sec_init();
 338 #endif
 339 #ifdef CONFIG_FSL_LS_PPA
 340         ppa_init();
 341 #endif
 342         return 0;
 343 }
 344
 345 int board_early_init_f(void)
 346 {
 347         fsl_lsch3_early_init_f();
 348         return 0;
 349 }
 350
 351 void detail_board_ddr_info(void)
 352 {
 353         puts("\nDDR    ");
 354         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 355         print_ddr_info(0);
 356 }
 357
 358 #if defined(CONFIG_ARCH_MISC_INIT)
 359 int arch_misc_init(void)
 360 {
 361         return 0;
 362 }
 363 #endif
 364
 365 #ifdef CONFIG_FSL_MC_ENET
 366 void fdt_fixup_board_enet(void *fdt)
 367 {
 368         int offset;
 369
 370         offset = fdt_path_offset(fdt, "/fsl-mc");
 371
 372         if (offset < 0)
 373                 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
 374
 375         if (offset < 0) {
 376                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 377                        __func__, offset);
 378                 return;
 379         }
 380
 381         if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
 382                 fdt_status_okay(fdt, offset);
 383         else
 384                 fdt_status_fail(fdt, offset);
 385 }
 386 #endif
 387
 388 #ifdef CONFIG_OF_BOARD_SETUP
 389 void fsl_fdt_fixup_flash(void *fdt)
 390 {
 391         int offset;
 392
 393 /*
 394  * IFC-NOR and QSPI are muxed on SoC.
 395  * So disable IFC node in dts if QSPI is enabled or
 396  * disable QSPI node in dts in case QSPI is not enabled.
 397  */
 398
 399 #ifdef CONFIG_FSL_QSPI
 400         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 401
 402         if (offset < 0)
 403                 offset = fdt_path_offset(fdt, "/ifc/nor");
 404 #else
 405         offset = fdt_path_offset(fdt, "/soc/quadspi");
 406
 407         if (offset < 0)
 408                 offset = fdt_path_offset(fdt, "/quadspi");
 409 #endif
 410         if (offset < 0)
 411                 return;
 412
 413         fdt_status_disabled(fdt, offset);
 414 }
 415
 416 int ft_board_setup(void *blob, bd_t *bd)
 417 {
 418         int err, i;
 419         u64 base[CONFIG_NR_DRAM_BANKS];
 420         u64 size[CONFIG_NR_DRAM_BANKS];
 421
 422         ft_cpu_setup(blob, bd);
 423
 424         /* fixup DT for the two GPP DDR banks */
 425         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 426                 base[i] = gd->bd->bi_dram[i].start;
 427                 size[i] = gd->bd->bi_dram[i].size;
 428         }
 429
 430 #ifdef CONFIG_RESV_RAM
 431         /* reduce size if reserved memory is within this bank */
 432         if (gd->arch.resv_ram >= base[0] &&
 433             gd->arch.resv_ram < base[0] + size[0])
 434                 size[0] = gd->arch.resv_ram - base[0];
 435         else if (gd->arch.resv_ram >= base[1] &&
 436                  gd->arch.resv_ram < base[1] + size[1])
 437                 size[1] = gd->arch.resv_ram - base[1];
 438 #endif
 439
 440         fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
 441
 442         fsl_fdt_fixup_flash(blob);
 443
 444 #ifdef CONFIG_FSL_MC_ENET
 445         fdt_fixup_board_enet(blob);
 446         err = fsl_mc_ldpaa_exit(bd);
 447         if (err)
 448                 return err;
 449 #endif
 450
 451         return 0;
 452 }
 453 #endif