2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
12 DECLARE_GLOBAL_DATA_PTR
;
14 void fsl_ddr_board_options(memctl_options_t
*popts
,
16 unsigned int ctrl_num
)
18 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
22 printf("Not supported controller number %d\n", ctrl_num
);
29 * we use identical timing for all slots. If needed, change the code
30 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
32 if (popts
->registered_dimm_en
)
33 pbsp
= rdimms
[ctrl_num
];
35 pbsp
= udimms
[ctrl_num
];
38 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
39 * freqency and n_banks specified in board_specific_parameters table.
41 ddr_freq
= get_ddr_freq(0) / 1000000;
42 while (pbsp
->datarate_mhz_high
) {
43 if (pbsp
->n_ranks
== pdimm
->n_ranks
&&
44 (pdimm
->rank_density
>> 30) >= pbsp
->rank_gb
) {
45 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
46 popts
->clk_adjust
= pbsp
->clk_adjust
;
47 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
48 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
49 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
58 printf("Error: board specific timing not found for data rate %lu MT/s\n"
59 "Trying to use the highest speed (%u) parameters\n",
60 ddr_freq
, pbsp_highest
->datarate_mhz_high
);
61 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
62 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
63 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
64 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
66 panic("DIMM is not supported by this board");
69 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
70 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
71 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
,
72 pbsp
->clk_adjust
, pbsp
->wrlvl_start
, pbsp
->wrlvl_ctl_2
,
74 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
75 if (ctrl_num
== CONFIG_DP_DDR_CTRL
) {
76 /* force DDR bus width to 32 bits */
77 popts
->data_bus_width
= 1;
78 popts
->otf_burst_chop_en
= 0;
79 popts
->burst_length
= DDR_BL8
;
80 popts
->bstopre
= 0; /* enable auto precharge */
84 * Factors to consider for half-strength driver enable:
85 * - number of DIMMs installed
87 popts
->half_strength_driver_enable
= 1;
89 * Write leveling override
91 popts
->wrlvl_override
= 1;
92 popts
->wrlvl_sample
= 0xf;
95 * Rtt and Rtt_WR override
97 popts
->rtt_override
= 0;
99 /* Enable ZQ calibration */
102 #ifdef CONFIG_SYS_FSL_DDR4
103 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_80ohm
);
104 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_80ohm
) |
105 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
107 /* DHC_EN =1, ODT = 75 Ohm */
108 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm
);
109 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_75ohm
);
113 #ifdef CONFIG_SYS_DDR_RAW_TIMING
114 dimm_params_t ddr_raw_timing
= {
116 .rank_density
= 1073741824u,
117 .capacity
= 2147483648,
118 .primary_sdram_width
= 64,
120 .registered_dimm
= 0,
124 .n_banks_per_sdram_device
= 8,
126 .burst_lengths_bitmask
= 0x0c,
129 .caslat_x
= 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
140 .refresh_rate_ps
= 7800000,
144 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
145 unsigned int controller_number
,
146 unsigned int dimm_number
)
148 const char dimm_model
[] = "Fixed DDR on board";
150 if (((controller_number
== 0) && (dimm_number
== 0)) ||
151 ((controller_number
== 1) && (dimm_number
== 0))) {
152 memcpy(pdimm
, &ddr_raw_timing
, sizeof(dimm_params_t
));
153 memset(pdimm
->mpart
, 0, sizeof(pdimm
->mpart
));
154 memcpy(pdimm
->mpart
, dimm_model
, sizeof(dimm_model
) - 1);
160 phys_size_t
initdram(int board_type
)
162 phys_size_t dram_size
;
164 puts("Initializing DDR....");
167 dram_size
= fsl_ddr_sdram();
172 void dram_init_banksize(void)
174 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
175 phys_size_t dp_ddr_size
;
178 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
179 if (gd
->ram_size
> CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
) {
180 gd
->bd
->bi_dram
[0].size
= CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
;
181 gd
->bd
->bi_dram
[1].start
= CONFIG_SYS_DDR_BLOCK2_BASE
;
182 gd
->bd
->bi_dram
[1].size
= gd
->ram_size
-
183 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
;
185 gd
->bd
->bi_dram
[0].size
= gd
->ram_size
;
188 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
189 /* initialize DP-DDR here */
192 * DDR controller use 0 as the base address for binding.
193 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
195 dp_ddr_size
= fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY
,
197 CONFIG_DP_DDR_NUM_CTRLS
,
198 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
,
201 gd
->bd
->bi_dram
[2].start
= CONFIG_SYS_DP_DDR_BASE
;
202 gd
->bd
->bi_dram
[2].size
= dp_ddr_size
;
204 puts("Not detected");