2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
15 #include <fsl-mc/fsl_mc.h>
16 #include <environment.h>
19 #include <asm/arch/soc.h>
22 #include <asm/arch/ppa.h>
25 #include "../common/qixis.h"
26 #include "ls2080aqds_qixis.h"
27 #include "../common/vid.h"
29 #define PIN_MUX_SEL_SDHC 0x00
30 #define PIN_MUX_SEL_DSPI 0x0a
31 #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
33 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
35 DECLARE_GLOBAL_DATA_PTR
;
42 unsigned long long get_qixis_addr(void)
44 unsigned long long addr
;
46 if (gd
->flags
& GD_FLG_RELOC
)
47 addr
= QIXIS_BASE_PHYS
;
49 addr
= QIXIS_BASE_PHYS_EARLY
;
52 * IFC address under 256MB is mapped to 0x30000000, any address above
53 * is mapped to 0x5_10000000 up to 4GB.
55 addr
= addr
> 0x10000000 ? addr
+ 0x500000000ULL
: addr
+ 0x30000000;
64 static const char *const freq
[] = {"100", "125", "156.25",
69 printf("Board: %s-QDS, ", buf
);
71 sw
= QIXIS_READ(arch
);
72 printf("Board Arch: V%d, ", sw
>> 4);
73 printf("Board version: %c, boot from ", (sw
& 0xf) + 'A' - 1);
75 memset((u8
*)buf
, 0x00, ARRAY_SIZE(buf
));
77 sw
= QIXIS_READ(brdcfg
[0]);
78 sw
= (sw
& QIXIS_LBMAP_MASK
) >> QIXIS_LBMAP_SHIFT
;
81 printf("vBank: %d\n", sw
);
91 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH
);
93 printf("FPGA: v%d (%s), build %d",
94 (int)QIXIS_READ(scver
), qixis_read_tag(buf
),
95 (int)qixis_read_minor());
96 /* the timestamp string contains "\n" at the end */
97 printf(" on %s", qixis_read_time(buf
));
100 * Display the actual SERDES reference clocks as configured by the
101 * dip switches on the board. Note that the SWx registers could
102 * technically be set to force the reference clocks to match the
103 * values that the SERDES expects (or vice versa). For now, however,
104 * we just display both values and hope the user notices when they
107 puts("SERDES1 Reference : ");
108 sw
= QIXIS_READ(brdcfg
[2]);
109 clock
= (sw
>> 6) & 3;
110 printf("Clock1 = %sMHz ", freq
[clock
]);
111 clock
= (sw
>> 4) & 3;
112 printf("Clock2 = %sMHz", freq
[clock
]);
114 puts("\nSERDES2 Reference : ");
115 clock
= (sw
>> 2) & 3;
116 printf("Clock1 = %sMHz ", freq
[clock
]);
117 clock
= (sw
>> 0) & 3;
118 printf("Clock2 = %sMHz\n", freq
[clock
]);
123 unsigned long get_board_sys_clk(void)
125 u8 sysclk_conf
= QIXIS_READ(brdcfg
[1]);
127 switch (sysclk_conf
& 0x0F) {
128 case QIXIS_SYSCLK_83
:
130 case QIXIS_SYSCLK_100
:
132 case QIXIS_SYSCLK_125
:
134 case QIXIS_SYSCLK_133
:
136 case QIXIS_SYSCLK_150
:
138 case QIXIS_SYSCLK_160
:
140 case QIXIS_SYSCLK_166
:
146 unsigned long get_board_ddr_clk(void)
148 u8 ddrclk_conf
= QIXIS_READ(brdcfg
[1]);
150 switch ((ddrclk_conf
& 0x30) >> 4) {
151 case QIXIS_DDRCLK_100
:
153 case QIXIS_DDRCLK_125
:
155 case QIXIS_DDRCLK_133
:
161 int select_i2c_ch_pca9547(u8 ch
)
165 ret
= i2c_write(I2C_MUX_PCA_ADDR_PRI
, 0, 1, &ch
, 1);
167 puts("PCA: failed to select proper channel\n");
174 int config_board_mux(int ctrl_type
)
178 reg5
= QIXIS_READ(brdcfg
[5]);
182 reg5
= SET_SDHC_MUX_SEL(reg5
, PIN_MUX_SEL_SDHC
);
185 reg5
= SET_SDHC_MUX_SEL(reg5
, PIN_MUX_SEL_DSPI
);
188 printf("Wrong mux interface type\n");
192 QIXIS_WRITE(brdcfg
[5], reg5
);
200 u32 __iomem
*dcfg_ccsr
= (u32 __iomem
*)DCFG_BASE
;
203 init_final_memctl_regs();
205 val
= in_le32(dcfg_ccsr
+ DCFG_RCWSR13
/ 4);
207 env_hwconfig
= env_get("hwconfig");
209 if (hwconfig_f("dspi", env_hwconfig
) &&
210 DCFG_RCWSR13_DSPI
== (val
& (u32
)(0xf << 8)))
211 config_board_mux(MUX_TYPE_DSPI
);
213 config_board_mux(MUX_TYPE_SDHC
);
215 #if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
216 val
= in_le32(dcfg_ccsr
+ DCFG_RCWSR15
/ 4);
218 if (DCFG_RCWSR15_IFCGRPABASE_QSPI
== (val
& (u32
)0x3))
219 QIXIS_WRITE(brdcfg
[9],
220 (QIXIS_READ(brdcfg
[9]) & 0xf8) |
221 FSL_QIXIS_BRDCFG9_QSPI
);
224 #ifdef CONFIG_ENV_IS_NOWHERE
225 gd
->env_addr
= (ulong
)&default_environment
[0];
227 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
228 rtc_enable_32khz_output();
229 #ifdef CONFIG_FSL_CAAM
233 #ifdef CONFIG_FSL_LS_PPA
240 int board_early_init_f(void)
242 #ifdef CONFIG_SYS_I2C_EARLY_INIT
245 fsl_lsch3_early_init_f();
246 #ifdef CONFIG_FSL_QSPI
247 /* input clk: 1/2 platform clk, output: input/20 */
248 out_le32(SCFG_BASE
+ SCFG_QSPICLKCTLR
, SCFG_QSPICLKCTRL_DIV_20
);
253 int misc_init_r(void)
256 printf("Warning: Adjusting core voltage failed.\n");
261 void detail_board_ddr_info(void)
264 print_size(gd
->bd
->bi_dram
[0].size
+ gd
->bd
->bi_dram
[1].size
, "");
266 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
267 if (soc_has_dp_ddr() && gd
->bd
->bi_dram
[2].size
) {
269 print_size(gd
->bd
->bi_dram
[2].size
, "");
270 print_ddr_info(CONFIG_DP_DDR_CTRL
);
275 #if defined(CONFIG_ARCH_MISC_INIT)
276 int arch_misc_init(void)
282 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
283 void fdt_fixup_board_enet(void *fdt
)
287 offset
= fdt_path_offset(fdt
, "/soc/fsl-mc");
290 offset
= fdt_path_offset(fdt
, "/fsl-mc");
293 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
298 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
299 fdt_status_okay(fdt
, offset
);
301 fdt_status_fail(fdt
, offset
);
304 void board_quiesce_devices(void)
306 fsl_mc_ldpaa_exit(gd
->bd
);
310 #ifdef CONFIG_OF_BOARD_SETUP
311 int ft_board_setup(void *blob
, bd_t
*bd
)
313 u64 base
[CONFIG_NR_DRAM_BANKS
];
314 u64 size
[CONFIG_NR_DRAM_BANKS
];
316 ft_cpu_setup(blob
, bd
);
318 /* fixup DT for the two GPP DDR banks */
319 base
[0] = gd
->bd
->bi_dram
[0].start
;
320 size
[0] = gd
->bd
->bi_dram
[0].size
;
321 base
[1] = gd
->bd
->bi_dram
[1].start
;
322 size
[1] = gd
->bd
->bi_dram
[1].size
;
324 #ifdef CONFIG_RESV_RAM
325 /* reduce size if reserved memory is within this bank */
326 if (gd
->arch
.resv_ram
>= base
[0] &&
327 gd
->arch
.resv_ram
< base
[0] + size
[0])
328 size
[0] = gd
->arch
.resv_ram
- base
[0];
329 else if (gd
->arch
.resv_ram
>= base
[1] &&
330 gd
->arch
.resv_ram
< base
[1] + size
[1])
331 size
[1] = gd
->arch
.resv_ram
- base
[1];
334 fdt_fixup_memory_banks(blob
, base
, size
, 2);
336 fsl_fdt_fixup_dr_usb(blob
, bd
);
338 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
339 fdt_fixup_board_enet(blob
);
346 void qixis_dump_switch(void)
350 QIXIS_WRITE(cms
[0], 0x00);
351 nr_of_cfgsw
= QIXIS_READ(cms
[1]);
353 puts("DIP switch settings dump:\n");
354 for (i
= 1; i
<= nr_of_cfgsw
; i
++) {
355 QIXIS_WRITE(cms
[0], i
);
356 printf("SW%d = (0x%02x)\n", i
, QIXIS_READ(cms
[1]));