board/freescale/ls2080ardb/ls2080ardb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <netdev.h>
  10 #include <fsl_ifc.h>
  11 #include <fsl_ddr.h>
  12 #include <asm/io.h>
  13 #include <hwconfig.h>
  14 #include <fdt_support.h>
  15 #include <libfdt.h>
  16 #include <fsl-mc/fsl_mc.h>
  17 #include <environment.h>
  18 #include <efi_loader.h>
  19 #include <i2c.h>
  20 #include <asm/arch/mmu.h>
  21 #include <asm/arch/soc.h>
  22 #include <fsl_sec.h>
  23
  24 #include "../common/qixis.h"
  25 #include "ls2080ardb_qixis.h"
  26 #include "../common/vid.h"
  27
  28 #define PIN_MUX_SEL_SDHC        0x00
  29 #define PIN_MUX_SEL_DSPI        0x0a
  30
  31 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0xf0) | value)
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 enum {
  35         MUX_TYPE_SDHC,
  36         MUX_TYPE_DSPI,
  37 };
  38
  39 unsigned long long get_qixis_addr(void)
  40 {
  41         unsigned long long addr;
  42
  43         if (gd->flags & GD_FLG_RELOC)
  44                 addr = QIXIS_BASE_PHYS;
  45         else
  46                 addr = QIXIS_BASE_PHYS_EARLY;
  47
  48         /*
  49          * IFC address under 256MB is mapped to 0x30000000, any address above
  50          * is mapped to 0x5_10000000 up to 4GB.
  51          */
  52         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  53
  54         return addr;
  55 }
  56
  57 int checkboard(void)
  58 {
  59         u8 sw;
  60         char buf[15];
  61
  62         cpu_name(buf);
  63         printf("Board: %s-RDB, ", buf);
  64
  65         sw = QIXIS_READ(arch);
  66         printf("Board Arch: V%d, ", sw >> 4);
  67         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  68
  69         sw = QIXIS_READ(brdcfg[0]);
  70         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  71
  72         if (sw < 0x8)
  73                 printf("vBank: %d\n", sw);
  74         else if (sw == 0x9)
  75                 puts("NAND\n");
  76         else
  77                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  78
  79         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  80
  81         puts("SERDES1 Reference : ");
  82         printf("Clock1 = 156.25MHz ");
  83         printf("Clock2 = 156.25MHz");
  84
  85         puts("\nSERDES2 Reference : ");
  86         printf("Clock1 = 100MHz ");
  87         printf("Clock2 = 100MHz\n");
  88
  89         return 0;
  90 }
  91
  92 unsigned long get_board_sys_clk(void)
  93 {
  94         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  95
  96         switch (sysclk_conf & 0x0F) {
  97         case QIXIS_SYSCLK_83:
  98                 return 83333333;
  99         case QIXIS_SYSCLK_100:
 100                 return 100000000;
 101         case QIXIS_SYSCLK_125:
 102                 return 125000000;
 103         case QIXIS_SYSCLK_133:
 104                 return 133333333;
 105         case QIXIS_SYSCLK_150:
 106                 return 150000000;
 107         case QIXIS_SYSCLK_160:
 108                 return 160000000;
 109         case QIXIS_SYSCLK_166:
 110                 return 166666666;
 111         }
 112         return 66666666;
 113 }
 114
 115 int select_i2c_ch_pca9547(u8 ch)
 116 {
 117         int ret;
 118
 119         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 120         if (ret) {
 121                 puts("PCA: failed to select proper channel\n");
 122                 return ret;
 123         }
 124
 125         return 0;
 126 }
 127
 128 int i2c_multiplexer_select_vid_channel(u8 channel)
 129 {
 130         return select_i2c_ch_pca9547(channel);
 131 }
 132
 133 int config_board_mux(int ctrl_type)
 134 {
 135         u8 reg5;
 136
 137         reg5 = QIXIS_READ(brdcfg[5]);
 138
 139         switch (ctrl_type) {
 140         case MUX_TYPE_SDHC:
 141                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 142                 break;
 143         case MUX_TYPE_DSPI:
 144                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
 145                 break;
 146         default:
 147                 printf("Wrong mux interface type\n");
 148                 return -1;
 149         }
 150
 151         QIXIS_WRITE(brdcfg[5], reg5);
 152
 153         return 0;
 154 }
 155
 156 int board_init(void)
 157 {
 158         char *env_hwconfig;
 159         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 160 #ifdef CONFIG_FSL_MC_ENET
 161         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 162 #endif
 163         u32 val;
 164
 165         init_final_memctl_regs();
 166
 167         val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
 168
 169         env_hwconfig = getenv("hwconfig");
 170
 171         if (hwconfig_f("dspi", env_hwconfig) &&
 172             DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
 173                 config_board_mux(MUX_TYPE_DSPI);
 174         else
 175                 config_board_mux(MUX_TYPE_SDHC);
 176
 177 #ifdef CONFIG_ENV_IS_NOWHERE
 178         gd->env_addr = (ulong)&default_environment[0];
 179 #endif
 180         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 181
 182         QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 183
 184 #ifdef CONFIG_FSL_MC_ENET
 185         /* invert AQR405 IRQ pins polarity */
 186         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 187 #endif
 188
 189         return 0;
 190 }
 191
 192 int board_early_init_f(void)
 193 {
 194         fsl_lsch3_early_init_f();
 195         return 0;
 196 }
 197
 198 int misc_init_r(void)
 199 {
 200         if (hwconfig("sdhc"))
 201                 config_board_mux(MUX_TYPE_SDHC);
 202
 203         if (adjust_vdd(0))
 204                 printf("Warning: Adjusting core voltage failed.\n");
 205
 206         return 0;
 207 }
 208
 209 void detail_board_ddr_info(void)
 210 {
 211         puts("\nDDR    ");
 212         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 213         print_ddr_info(0);
 214 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 215         if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 216                 puts("\nDP-DDR ");
 217                 print_size(gd->bd->bi_dram[2].size, "");
 218                 print_ddr_info(CONFIG_DP_DDR_CTRL);
 219         }
 220 #endif
 221 }
 222
 223 #if defined(CONFIG_ARCH_MISC_INIT)
 224 int arch_misc_init(void)
 225 {
 226 #ifdef CONFIG_FSL_CAAM
 227         sec_init();
 228 #endif
 229         return 0;
 230 }
 231 #endif
 232
 233 #ifdef CONFIG_FSL_MC_ENET
 234 void fdt_fixup_board_enet(void *fdt)
 235 {
 236         int offset;
 237
 238         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 239
 240         if (offset < 0)
 241                 offset = fdt_path_offset(fdt, "/fsl-mc");
 242
 243         if (offset < 0) {
 244                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 245                        __func__, offset);
 246                 return;
 247         }
 248
 249         if (get_mc_boot_status() == 0)
 250                 fdt_status_okay(fdt, offset);
 251         else
 252                 fdt_status_fail(fdt, offset);
 253 }
 254
 255 void board_quiesce_devices(void)
 256 {
 257         fsl_mc_ldpaa_exit(gd->bd);
 258 }
 259 #endif
 260
 261 #ifdef CONFIG_OF_BOARD_SETUP
 262 int ft_board_setup(void *blob, bd_t *bd)
 263 {
 264         u64 base[CONFIG_NR_DRAM_BANKS];
 265         u64 size[CONFIG_NR_DRAM_BANKS];
 266
 267         ft_cpu_setup(blob, bd);
 268
 269         /* fixup DT for the two GPP DDR banks */
 270         base[0] = gd->bd->bi_dram[0].start;
 271         size[0] = gd->bd->bi_dram[0].size;
 272         base[1] = gd->bd->bi_dram[1].start;
 273         size[1] = gd->bd->bi_dram[1].size;
 274
 275 #ifdef CONFIG_RESV_RAM
 276         /* reduce size if reserved memory is within this bank */
 277         if (gd->arch.resv_ram >= base[0] &&
 278             gd->arch.resv_ram < base[0] + size[0])
 279                 size[0] = gd->arch.resv_ram - base[0];
 280         else if (gd->arch.resv_ram >= base[1] &&
 281                  gd->arch.resv_ram < base[1] + size[1])
 282                 size[1] = gd->arch.resv_ram - base[1];
 283 #endif
 284
 285         fdt_fixup_memory_banks(blob, base, size, 2);
 286
 287         fsl_fdt_fixup_dr_usb(blob, bd);
 288
 289 #ifdef CONFIG_FSL_MC_ENET
 290         fdt_fixup_board_enet(blob);
 291 #endif
 292
 293         return 0;
 294 }
 295 #endif
 296
 297 void qixis_dump_switch(void)
 298 {
 299         int i, nr_of_cfgsw;
 300
 301         QIXIS_WRITE(cms[0], 0x00);
 302         nr_of_cfgsw = QIXIS_READ(cms[1]);
 303
 304         puts("DIP switch settings dump:\n");
 305         for (i = 1; i <= nr_of_cfgsw; i++) {
 306                 QIXIS_WRITE(cms[0], i);
 307                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 308         }
 309 }
 310
 311 /*
 312  * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 313  * Both slots has 0x54, resulting 2nd slot unusable.
 314  */
 315 void update_spd_address(unsigned int ctrl_num,
 316                         unsigned int slot,
 317                         unsigned int *addr)
 318 {
 319         u8 sw;
 320
 321         sw = QIXIS_READ(arch);
 322         if ((sw & 0xf) < 0x3) {
 323                 if (ctrl_num == 1 && slot == 0)
 324                         *addr = SPD_EEPROM_ADDRESS4;
 325                 else if (ctrl_num == 1 && slot == 1)
 326                         *addr = SPD_EEPROM_ADDRESS3;
 327         }
 328 }