board/freescale/ls2085aqds/ls2085aqds.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <netdev.h>
  10 #include <fsl_ifc.h>
  11 #include <fsl_ddr.h>
  12 #include <asm/io.h>
  13 #include <fdt_support.h>
  14 #include <libfdt.h>
  15 #include <fsl_debug_server.h>
  16 #include <fsl-mc/fsl_mc.h>
  17 #include <environment.h>
  18 #include <i2c.h>
  19 #include <rtc.h>
  20 #include <asm/arch-fsl-lsch3/soc.h>
  21 #include <hwconfig.h>
  22
  23 #include "../common/qixis.h"
  24 #include "ls2085aqds_qixis.h"
  25
  26 #define PIN_MUX_SEL_SDHC        0x00
  27 #define PIN_MUX_SEL_DSPI        0x0a
  28
  29 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0xf0) | value)
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 enum {
  34         MUX_TYPE_SDHC,
  35         MUX_TYPE_DSPI,
  36 };
  37
  38 unsigned long long get_qixis_addr(void)
  39 {
  40         unsigned long long addr;
  41
  42         if (gd->flags & GD_FLG_RELOC)
  43                 addr = QIXIS_BASE_PHYS;
  44         else
  45                 addr = QIXIS_BASE_PHYS_EARLY;
  46
  47         /*
  48          * IFC address under 256MB is mapped to 0x30000000, any address above
  49          * is mapped to 0x5_10000000 up to 4GB.
  50          */
  51         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  52
  53         return addr;
  54 }
  55
  56 int checkboard(void)
  57 {
  58         char buf[64];
  59         u8 sw;
  60         static const char *const freq[] = {"100", "125", "156.25",
  61                                             "100 separate SSCG"};
  62         int clock;
  63
  64         cpu_name(buf);
  65         printf("Board: %s-QDS, ", buf);
  66
  67         sw = QIXIS_READ(arch);
  68         printf("Board Arch: V%d, ", sw >> 4);
  69         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  70
  71         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  72
  73         sw = QIXIS_READ(brdcfg[0]);
  74         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  75
  76         if (sw < 0x8)
  77                 printf("vBank: %d\n", sw);
  78         else if (sw == 0x8)
  79                 puts("PromJet\n");
  80         else if (sw == 0x9)
  81                 puts("NAND\n");
  82         else if (sw == 0x15)
  83                 printf("IFCCard\n");
  84         else
  85                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  86
  87         printf("FPGA: v%d (%s), build %d",
  88                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  89                (int)qixis_read_minor());
  90         /* the timestamp string contains "\n" at the end */
  91         printf(" on %s", qixis_read_time(buf));
  92
  93         /*
  94          * Display the actual SERDES reference clocks as configured by the
  95          * dip switches on the board.  Note that the SWx registers could
  96          * technically be set to force the reference clocks to match the
  97          * values that the SERDES expects (or vice versa).  For now, however,
  98          * we just display both values and hope the user notices when they
  99          * don't match.
 100          */
 101         puts("SERDES1 Reference : ");
 102         sw = QIXIS_READ(brdcfg[2]);
 103         clock = (sw >> 6) & 3;
 104         printf("Clock1 = %sMHz ", freq[clock]);
 105         clock = (sw >> 4) & 3;
 106         printf("Clock2 = %sMHz", freq[clock]);
 107
 108         puts("\nSERDES2 Reference : ");
 109         clock = (sw >> 2) & 3;
 110         printf("Clock1 = %sMHz ", freq[clock]);
 111         clock = (sw >> 0) & 3;
 112         printf("Clock2 = %sMHz\n", freq[clock]);
 113
 114         return 0;
 115 }
 116
 117 unsigned long get_board_sys_clk(void)
 118 {
 119         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 120
 121         switch (sysclk_conf & 0x0F) {
 122         case QIXIS_SYSCLK_83:
 123                 return 83333333;
 124         case QIXIS_SYSCLK_100:
 125                 return 100000000;
 126         case QIXIS_SYSCLK_125:
 127                 return 125000000;
 128         case QIXIS_SYSCLK_133:
 129                 return 133333333;
 130         case QIXIS_SYSCLK_150:
 131                 return 150000000;
 132         case QIXIS_SYSCLK_160:
 133                 return 160000000;
 134         case QIXIS_SYSCLK_166:
 135                 return 166666666;
 136         }
 137         return 66666666;
 138 }
 139
 140 unsigned long get_board_ddr_clk(void)
 141 {
 142         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 143
 144         switch ((ddrclk_conf & 0x30) >> 4) {
 145         case QIXIS_DDRCLK_100:
 146                 return 100000000;
 147         case QIXIS_DDRCLK_125:
 148                 return 125000000;
 149         case QIXIS_DDRCLK_133:
 150                 return 133333333;
 151         }
 152         return 66666666;
 153 }
 154
 155 int select_i2c_ch_pca9547(u8 ch)
 156 {
 157         int ret;
 158
 159         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 160         if (ret) {
 161                 puts("PCA: failed to select proper channel\n");
 162                 return ret;
 163         }
 164
 165         return 0;
 166 }
 167
 168 int config_board_mux(int ctrl_type)
 169 {
 170         u8 reg5;
 171
 172         reg5 = QIXIS_READ(brdcfg[5]);
 173
 174         switch (ctrl_type) {
 175         case MUX_TYPE_SDHC:
 176                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 177                 break;
 178         case MUX_TYPE_DSPI:
 179                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
 180                 break;
 181         default:
 182                 printf("Wrong mux interface type\n");
 183                 return -1;
 184         }
 185
 186         QIXIS_WRITE(brdcfg[5], reg5);
 187
 188         return 0;
 189 }
 190
 191 int board_init(void)
 192 {
 193         char *env_hwconfig;
 194         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 195         u32 val;
 196
 197         init_final_memctl_regs();
 198
 199         val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
 200
 201         env_hwconfig = getenv("hwconfig");
 202
 203         if (hwconfig_f("dspi", env_hwconfig) &&
 204             DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
 205                 config_board_mux(MUX_TYPE_DSPI);
 206         else
 207                 config_board_mux(MUX_TYPE_SDHC);
 208
 209 #ifdef CONFIG_ENV_IS_NOWHERE
 210         gd->env_addr = (ulong)&default_environment[0];
 211 #endif
 212         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 213         rtc_enable_32khz_output();
 214
 215         return 0;
 216 }
 217
 218 int board_early_init_f(void)
 219 {
 220         fsl_lsch3_early_init_f();
 221         return 0;
 222 }
 223
 224 void detail_board_ddr_info(void)
 225 {
 226         puts("\nDDR    ");
 227         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 228         print_ddr_info(0);
 229         if (gd->bd->bi_dram[2].size) {
 230                 puts("\nDP-DDR ");
 231                 print_size(gd->bd->bi_dram[2].size, "");
 232                 print_ddr_info(CONFIG_DP_DDR_CTRL);
 233         }
 234 }
 235
 236 int dram_init(void)
 237 {
 238         gd->ram_size = initdram(0);
 239
 240         return 0;
 241 }
 242
 243 #if defined(CONFIG_ARCH_MISC_INIT)
 244 int arch_misc_init(void)
 245 {
 246 #ifdef CONFIG_FSL_DEBUG_SERVER
 247         debug_server_init();
 248 #endif
 249
 250         return 0;
 251 }
 252 #endif
 253
 254 unsigned long get_dram_size_to_hide(void)
 255 {
 256         unsigned long dram_to_hide = 0;
 257
 258 /* Carve the Debug Server private DRAM block from the end of DRAM */
 259 #ifdef CONFIG_FSL_DEBUG_SERVER
 260         dram_to_hide += debug_server_get_dram_block_size();
 261 #endif
 262
 263 /* Carve the MC private DRAM block from the end of DRAM */
 264 #ifdef CONFIG_FSL_MC_ENET
 265         dram_to_hide += mc_get_dram_block_size();
 266 #endif
 267
 268         return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
 269 }
 270
 271 #ifdef CONFIG_FSL_MC_ENET
 272 void fdt_fixup_board_enet(void *fdt)
 273 {
 274         int offset;
 275
 276         offset = fdt_path_offset(fdt, "/fsl-mc");
 277
 278         if (offset < 0)
 279                 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
 280
 281         if (offset < 0) {
 282                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 283                        __func__, offset);
 284                 return;
 285         }
 286
 287         if (get_mc_boot_status() == 0)
 288                 fdt_status_okay(fdt, offset);
 289         else
 290                 fdt_status_fail(fdt, offset);
 291 }
 292 #endif
 293
 294 #ifdef CONFIG_OF_BOARD_SETUP
 295 int ft_board_setup(void *blob, bd_t *bd)
 296 {
 297         u64 base[CONFIG_NR_DRAM_BANKS];
 298         u64 size[CONFIG_NR_DRAM_BANKS];
 299
 300         ft_cpu_setup(blob, bd);
 301
 302         /* fixup DT for the two GPP DDR banks */
 303         base[0] = gd->bd->bi_dram[0].start;
 304         size[0] = gd->bd->bi_dram[0].size;
 305         base[1] = gd->bd->bi_dram[1].start;
 306         size[1] = gd->bd->bi_dram[1].size;
 307
 308         fdt_fixup_memory_banks(blob, base, size, 2);
 309
 310 #ifdef CONFIG_FSL_MC_ENET
 311         fdt_fixup_board_enet(blob);
 312         fsl_mc_ldpaa_exit(bd);
 313 #endif
 314
 315         return 0;
 316 }
 317 #endif
 318
 319 void qixis_dump_switch(void)
 320 {
 321         int i, nr_of_cfgsw;
 322
 323         QIXIS_WRITE(cms[0], 0x00);
 324         nr_of_cfgsw = QIXIS_READ(cms[1]);
 325
 326         puts("DIP switch settings dump:\n");
 327         for (i = 1; i <= nr_of_cfgsw; i++) {
 328                 QIXIS_WRITE(cms[0], i);
 329                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 330         }
 331 }