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git.ipfire.org Git - thirdparty/u-boot.git/blob - board/freescale/m5235evb/m5235evb.c
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/immap.h>
16 DECLARE_GLOBAL_DATA_PTR
;
21 puts("Freescale M5235 EVB\n");
25 phys_size_t
initdram(int board_type
)
27 sdram_t
*sdram
= (sdram_t
*)(MMAP_SDRAM
);
28 gpio_t
*gpio
= (gpio_t
*)(MMAP_GPIO
);
29 u32 dramsize
, i
, dramclk
;
32 * When booting from external Flash, the port-size is less than
33 * the port-size of SDRAM. In this case it is necessary to enable
34 * Data[15:0] on Port Address/Data.
37 GPIO_PAR_AD_ADDR23
| GPIO_PAR_AD_ADDR22
| GPIO_PAR_AD_ADDR21
|
40 /* Initialize PAR to enable SDRAM signals */
41 out_8(&gpio
->par_sdram
,
42 GPIO_PAR_SDRAM_SDWE
| GPIO_PAR_SDRAM_SCAS
|
43 GPIO_PAR_SDRAM_SRAS
| GPIO_PAR_SDRAM_SCKE
|
44 GPIO_PAR_SDRAM_SDCS(3));
46 dramsize
= CONFIG_SYS_SDRAM_SIZE
* 0x100000;
47 for (i
= 0x13; i
< 0x20; i
++) {
48 if (dramsize
== (1 << i
))
53 if (!(in_be32(&sdram
->dacr0
) & SDRAMC_DARCn_RE
)) {
54 dramclk
= gd
->bus_clk
/ (CONFIG_SYS_HZ
* CONFIG_SYS_HZ
);
56 /* Initialize DRAM Control Register: DCR */
57 out_be16(&sdram
->dcr
, SDRAMC_DCR_RTIM_9CLKS
|
58 SDRAMC_DCR_RTIM_6CLKS
|
59 SDRAMC_DCR_RC((15 * dramclk
) >> 4));
61 /* Initialize DACR0 */
62 out_be32(&sdram
->dacr0
,
63 SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE
) |
64 SDRAMC_DARCn_CASL_C1
| SDRAMC_DARCn_CBM_CMD20
|
69 out_be32(&sdram
->dmr0
,
70 ((dramsize
- 1) & 0xFFFC0000) | SDRAMC_DMRn_V
);
73 /* Set IP (bit 3) in DACR */
74 setbits_be32(&sdram
->dacr0
, SDRAMC_DARCn_IP
);
76 /* Wait 30ns to allow banks to precharge */
77 for (i
= 0; i
< 5; i
++) {
81 /* Write to this block to initiate precharge */
82 *(u32
*) (CONFIG_SYS_SDRAM_BASE
) = 0xA5A59696;
84 /* Set RE (bit 15) in DACR */
85 setbits_be32(&sdram
->dacr0
, SDRAMC_DARCn_RE
);
87 /* Wait for at least 8 auto refresh cycles to occur */
88 for (i
= 0; i
< 0x2000; i
++) {
92 /* Finish the configuration by issuing the MRS. */
93 setbits_be32(&sdram
->dacr0
, SDRAMC_DARCn_IMRS
);
96 /* Write to the SDRAM Mode Register */
97 *(u32
*) (CONFIG_SYS_SDRAM_BASE
+ 0x400) = 0xA5A59696;
105 /* TODO: XXX XXX XXX */
106 printf("DRAM test not implemented!\n");