2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/immap.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
37 int fecpin_setclear(struct eth_device
*dev
, int setclear
)
39 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
43 (GPIO_PAR_FECI2C_EMDC_FECEMDC
| GPIO_PAR_FECI2C_EMDIO_FECEMDIO
);
46 ~(GPIO_PAR_FECI2C_EMDC_MASK
| GPIO_PAR_FECI2C_EMDIO_MASK
);
52 #if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
55 /* Make MII read/write commands for the FEC. */
56 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
58 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
60 /* PHY identification */
61 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
62 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
63 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
64 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
65 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
66 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
67 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
68 #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
69 #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
70 #define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
72 #define STR_ID_LXT970 "LXT970"
73 #define STR_ID_LXT971 "LXT971"
74 #define STR_ID_82555 "Intel82555"
75 #define STR_ID_QS6612 "QS6612"
76 #define STR_ID_AMD79C784 "AMD79C784"
77 #define STR_ID_LSI80225 "LSI80225"
78 #define STR_ID_LSI80225B "LSI80225/B"
79 #define STR_ID_DP83848VV "N83848"
80 #define STR_ID_DP83849 "N83849"
81 #define STR_ID_KS8721BL "KS8721BL"
83 /****************************************************************************
84 * mii_init -- Initialize the MII for MII command without ethernet
85 * This function is a subset of eth_init
86 ****************************************************************************
88 void mii_reset(struct fec_info_s
*info
)
90 volatile fec_t
*fecp
= (fec_t
*) (info
->miibase
);
93 fecp
->ecr
= FEC_ECR_RESET
;
94 for (i
= 0; (fecp
->ecr
& FEC_ECR_RESET
) && (i
< FEC_RESET_DELAY
); ++i
) {
97 if (i
== FEC_RESET_DELAY
) {
98 printf("FEC_RESET_DELAY timeout\n");
102 /* send command to phy using mii, wait for result */
103 uint
mii_send(uint mii_cmd
)
105 struct fec_info_s
*info
;
106 struct eth_device
*dev
;
111 /* retrieve from register structure */
115 ep
= (fec_t
*) info
->miibase
;
117 ep
->mmfr
= mii_cmd
; /* command to phy */
119 /* wait for mii complete */
120 while (!(ep
->eir
& FEC_EIR_MII
) && (j
< MCFFEC_TOUT_LOOP
)) {
124 if (j
>= MCFFEC_TOUT_LOOP
) {
125 printf("MII not complete\n");
129 mii_reply
= ep
->mmfr
; /* result from phy */
130 ep
->eir
= FEC_EIR_MII
; /* clear MII complete */
132 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
133 __FILE__
, __LINE__
, __FUNCTION__
, mii_cmd
, mii_reply
);
136 return (mii_reply
& 0xffff); /* data read from phy */
138 #endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
140 #if defined(CFG_DISCOVER_PHY)
141 int mii_discover_phy(struct eth_device
*dev
)
143 #define MAX_PHY_PASSES 11
144 struct fec_info_s
*info
= dev
->priv
;
148 if (info
->phyname_init
)
149 return info
->phy_addr
;
151 phyaddr
= -1; /* didn't find a PHY yet */
152 for (pass
= 1; pass
<= MAX_PHY_PASSES
&& phyaddr
< 0; ++pass
) {
154 /* PHY may need more time to recover from reset.
155 * The LXT970 needs 50ms typical, no maximum is
156 * specified, so wait 10ms before try again.
157 * With 11 passes this gives it 100ms to wake up.
159 udelay(10000); /* wait 10ms */
162 for (phyno
= 0; phyno
< 32 && phyaddr
< 0; ++phyno
) {
164 phytype
= mii_send(mk_mii_read(phyno
, PHY_PHYIDR1
));
166 printf("PHY type 0x%x pass %d type\n", phytype
, pass
);
168 if (phytype
!= 0xffff) {
172 mii_send(mk_mii_read(phyno
, PHY_PHYIDR2
));
174 switch (phytype
& 0xffffffff) {
175 case PHY_ID_KS8721BL
:
176 strcpy(info
->phy_name
,
178 info
->phyname_init
= 1;
181 strcpy(info
->phy_name
, "unknown");
182 info
->phyname_init
= 1;
187 printf("PHY @ 0x%x pass %d type ", phyno
, pass
);
188 switch (phytype
& 0xffffffff) {
189 case PHY_ID_KS8721BL
:
190 printf(STR_ID_KS8721BL
);
193 printf("0x%08x\n", phytype
);
201 printf("No PHY device found.\n");
205 #endif /* CFG_DISCOVER_PHY */
207 void mii_init(void) __attribute__((weak
,alias("__mii_init")));
209 void __mii_init(void)
211 volatile fec_t
*fecp
;
212 struct fec_info_s
*info
;
213 struct eth_device
*dev
;
214 int miispd
= 0, i
= 0;
217 /* retrieve from register structure */
221 fecp
= (fec_t
*) info
->miibase
;
223 fecpin_setclear(dev
, 1);
227 /* We use strictly polling mode only */
230 /* Clear any pending interrupt */
231 fecp
->eir
= 0xffffffff;
234 miispd
= (gd
->bus_clk
/ 1000000) / 5;
235 fecp
->mscr
= miispd
<< 1;
237 info
->phy_addr
= mii_discover_phy(dev
);
239 #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
240 while (i
< MCFFEC_TOUT_LOOP
) {
242 miiphy_read(dev
->name
, info
->phy_addr
, PHY_BMSR
, &autoneg
);
245 if ((autoneg
& AUTONEGLINK
) == AUTONEGLINK
)
250 if (i
>= MCFFEC_TOUT_LOOP
) {
251 printf("Auto Negotiation not complete\n");
254 /* adapt to the half/full speed settings */
255 info
->dup_spd
= miiphy_duplex(dev
->name
, info
->phy_addr
) << 16;
256 info
->dup_spd
|= miiphy_speed(dev
->name
, info
->phy_addr
);
259 /*****************************************************************************
260 * Read and write a MII PHY register, routines used by MII Utilities
262 * FIXME: These routines are expected to return 0 on success, but mii_send
263 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
264 * no PHY connected...
265 * For now always return 0.
266 * FIXME: These routines only work after calling eth_init() at least once!
267 * Otherwise they hang in mii_send() !!! Sorry!
268 *****************************************************************************/
270 int mcffec_miiphy_read(char *devname
, unsigned char addr
, unsigned char reg
,
271 unsigned short *value
)
273 short rdreg
; /* register working value */
276 printf("miiphy_read(0x%x) @ 0x%x = ", reg
, addr
);
278 rdreg
= mii_send(mk_mii_read(addr
, reg
));
283 printf("0x%04x\n", *value
);
289 int mcffec_miiphy_write(char *devname
, unsigned char addr
, unsigned char reg
,
290 unsigned short value
)
292 short rdreg
; /* register working value */
295 printf("miiphy_write(0x%x) @ 0x%x = ", reg
, addr
);
298 rdreg
= mii_send(mk_mii_write(addr
, reg
, value
));
301 printf("0x%04x\n", value
);
307 #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */