board/freescale/m5249evb/m5249evb.c

   1 /*
   2  * (C) Copyright 2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <malloc.h>
  11 #include <asm/immap.h>
  12
  13 int checkboard (void) {
  14         ulong val;
  15         uchar val8;
  16
  17         puts ("Board: ");
  18         puts("Freescale M5249EVB");
  19         val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
  20         printf(" (Switch=%1X)\n", val8);
  21
  22         /*
  23          * Set LED on
  24          */
  25         val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
  26         mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
  27
  28         return 0;
  29 };
  30
  31
  32 phys_size_t initdram (int board_type) {
  33         unsigned long   junk = 0xa5a59696;
  34
  35         /*
  36          *  Note:
  37          *      RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
  38          */
  39
  40 #ifdef CONFIG_SYS_FAST_CLK
  41         /*
  42          * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
  43          * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
  44          */
  45         mbar_writeShort(MCFSIM_DCR, 0x8239);
  46 #elif CONFIG_SYS_PLL_BYPASS
  47         /*
  48          * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
  49          * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
  50          */
  51         mbar_writeShort(MCFSIM_DCR, 0x8202);
  52 #else
  53         /*
  54          * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
  55          * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
  56          */
  57         mbar_writeShort(MCFSIM_DCR, 0x8222);
  58 #endif
  59
  60         /*
  61          * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
  62          * PM=1 (continuous page mode)
  63          */
  64
  65         /* RE=0 (keep auto-refresh disabled while setting up registers) */
  66         mbar_writeLong(MCFSIM_DACR0, 0x00003324);
  67
  68         /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
  69         mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
  70
  71         /** Precharge sequence **/
  72         mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
  73         *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
  74         udelay(0x10); /* Allow several Precharge cycles */
  75
  76         /** Refresh Sequence **/
  77         mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
  78         udelay(0x7d0); /* Allow gobs of refresh cycles */
  79
  80         /** Mode Register initialization **/
  81         mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
  82         *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
  83
  84         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  85 };
  86
  87
  88 int testdram (void) {
  89         /* TODO: XXX XXX XXX */
  90         printf ("DRAM test not implemented!\n");
  91
  92         return (0);
  93 }