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git.ipfire.org Git - thirdparty/u-boot.git/blob - board/freescale/m5253demo/m5253demo.c
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * Hayden Fraser (Hayden.Fraser@freescale.com)
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/immap.h>
19 puts("Freescale MCF5253 DEMO\n");
23 phys_size_t
initdram(int board_type
)
28 * Check to see if the SDRAM has already been initialized
29 * by a run control tool
31 if (!(mbar_readLong(MCFSIM_DCR
) & 0x8000)) {
34 RC
= (CONFIG_SYS_CLK
/ 1000000) >> 1;
37 /* Initialize DRAM Control Register: DCR */
38 mbar_writeShort(MCFSIM_DCR
, (0x8400 | RC
));
41 mbar_writeLong(MCFSIM_DACR0
, 0x00003224);
45 dramsize
= (CONFIG_SYS_SDRAM_SIZE
<< 20);
46 temp
= (dramsize
- 1) & 0xFFFC0000;
47 mbar_writeLong(MCFSIM_DMR0
, temp
| 1);
50 mbar_writeLong(MCFSIM_DACR0
, 0x0000322c);
54 /* Write to this block to initiate precharge */
55 *(u32
*) (CONFIG_SYS_SDRAM_BASE
) = 0xa5a5a5a5;
59 /* Set RE bit in DACR */
60 mbar_writeLong(MCFSIM_DACR0
,
61 mbar_readLong(MCFSIM_DACR0
) | 0x8000);
64 /* Wait for at least 8 auto refresh cycles to occur */
67 /* Finish the configuration by issuing the MRS */
68 mbar_writeLong(MCFSIM_DACR0
,
69 mbar_readLong(MCFSIM_DACR0
) | 0x0040);
72 *(u32
*) (CONFIG_SYS_SDRAM_BASE
+ 0x800) = 0xa5a5a5a5;
81 /* TODO: XXX XXX XXX */
82 printf("DRAM test not implemented!\n");
94 void ide_set_reset(int idereset
)
96 atac_t
*ata
= (atac_t
*) CONFIG_SYS_ATA_BASE_ADDR
;
98 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
99 int piotms
[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
100 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
101 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
102 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
103 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
111 mbar2_writeLong(CIM_MISCCR
, CIM_MISCCR_CPUEND
);
113 #define CALC_TIMING(t) (t + period - 1) / period
114 period
= 1000000000 / (CONFIG_SYS_CLK
/ 2); /* period in ns */
116 /*ata->ton = CALC_TIMING (180); */
117 out_8(&ata
->t1
, CALC_TIMING(piotms
[2][0]));
118 out_8(&ata
->t2w
, CALC_TIMING(piotms
[2][1]));
119 out_8(&ata
->t2r
, CALC_TIMING(piotms
[2][1]));
120 out_8(&ata
->ta
, CALC_TIMING(piotms
[2][8]));
121 out_8(&ata
->trd
, CALC_TIMING(piotms
[2][7]));
122 out_8(&ata
->t4
, CALC_TIMING(piotms
[2][3]));
123 out_8(&ata
->t9
, CALC_TIMING(piotms
[2][6]));
126 out_8(&ata
->cr
, 0x40);
129 setbits_8(&ata
->cr
, 0x01);
132 #endif /* CONFIG_CMD_IDE */
135 #ifdef CONFIG_DRIVER_DM9000
136 int board_eth_init(bd_t
*bis
)
138 return dm9000_initialize(bis
);