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git.ipfire.org Git - people/ms/u-boot.git/blob - board/freescale/m5253evbe/m5253evbe.c
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * Hayden Fraser (Hayden.Fraser@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/immap.h>
33 puts("Freescale MCF5253 EVBE\n");
37 phys_size_t
initdram(int board_type
)
40 * Check to see if the SDRAM has already been initialized
41 * by a run control tool
43 if (!(mbar_readLong(MCFSIM_DCR
) & 0x8000)) {
46 RC
= (CONFIG_SYS_CLK
/ 1000000) >> 1;
49 /* Initialize DRAM Control Register: DCR */
50 mbar_writeShort(MCFSIM_DCR
, (0x8400 | RC
));
53 mbar_writeLong(MCFSIM_DACR0
, 0x00002320);
57 dramsize
= ((CONFIG_SYS_SDRAM_SIZE
<< 20) - 1) & 0xFFFC0000;
58 mbar_writeLong(MCFSIM_DMR0
, dramsize
| 1);
61 mbar_writeLong(MCFSIM_DACR0
, 0x00002328);
64 /* Write to this block to initiate precharge */
65 *(u32
*) (CONFIG_SYS_SDRAM_BASE
) = 0xa5a5a5a5;
68 /* Set RE bit in DACR */
69 mbar_writeLong(MCFSIM_DACR0
,
70 mbar_readLong(MCFSIM_DACR0
) | 0x8000);
73 /* Wait for at least 8 auto refresh cycles to occur */
76 /* Finish the configuration by issuing the MRS */
77 mbar_writeLong(MCFSIM_DACR0
,
78 mbar_readLong(MCFSIM_DACR0
) | 0x0040);
81 *(u32
*) (CONFIG_SYS_SDRAM_BASE
+ 0x800) = 0xa5a5a5a5;
84 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
89 /* TODO: XXX XXX XXX */
90 printf("DRAM test not implemented!\n");
102 void ide_set_reset(int idereset
)
104 volatile atac_t
*ata
= (atac_t
*) CONFIG_SYS_ATA_BASE_ADDR
;
106 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
107 int piotms
[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
108 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
109 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
110 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
111 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
115 ata
->cr
= 0; /* control reset */
118 mbar2_writeLong(CIM_MISCCR
, CIM_MISCCR_CPUEND
);
120 #define CALC_TIMING(t) (t + period - 1) / period
121 period
= 1000000000 / (CONFIG_SYS_CLK
/ 2); /* period in ns */
123 /*ata->ton = CALC_TIMING (180); */
124 ata
->t1
= CALC_TIMING(piotms
[2][0]);
125 ata
->t2w
= CALC_TIMING(piotms
[2][1]);
126 ata
->t2r
= CALC_TIMING(piotms
[2][1]);
127 ata
->ta
= CALC_TIMING(piotms
[2][8]);
128 ata
->trd
= CALC_TIMING(piotms
[2][7]);
129 ata
->t4
= CALC_TIMING(piotms
[2][3]);
130 ata
->t9
= CALC_TIMING(piotms
[2][6]);
132 ata
->cr
= 0x40; /* IORDY enable */
134 ata
->cr
|= 0x01; /* IORDY enable */
137 #endif /* CONFIG_CMD_IDE */