board/freescale/m5253evbe/m5253evbe.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * Hayden Fraser (Hayden.Fraser@freescale.com)
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <asm/immap.h>
  29
  30 int checkboard(void)
  31 {
  32         puts("Board: ");
  33         puts("Freescale MCF5253 EVBE\n");
  34         return 0;
  35 };
  36
  37 long int initdram(int board_type)
  38 {
  39         int i;
  40
  41         /*
  42          * Check to see if the SDRAM has already been initialized
  43          * by a run control tool
  44          */
  45         if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
  46                 u32 RC, dramsize;
  47
  48                 RC = (CFG_CLK / 1000000) >> 1;
  49                 RC = (RC * 15) >> 4;
  50
  51                 /* Initialize DRAM Control Register: DCR */
  52                 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
  53
  54                 mbar_writeLong(MCFSIM_DACR0, 0x00003224);
  55
  56                 /* Initialize DMR0 */
  57                 dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
  58                 mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
  59
  60                 mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
  61
  62                 /* Write to this block to initiate precharge */
  63                 *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
  64
  65                 /* Set RE bit in DACR */
  66                 mbar_writeLong(MCFSIM_DACR0,
  67                                mbar_readLong(MCFSIM_DACR0) | 0x8000);
  68
  69                 /* Wait for at least 8 auto refresh cycles to occur */
  70                 udelay(500);
  71
  72                 /* Finish the configuration by issuing the MRS */
  73                 mbar_writeLong(MCFSIM_DACR0,
  74                                mbar_readLong(MCFSIM_DACR0) | 0x0040);
  75
  76                 *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
  77         }
  78
  79         return CFG_SDRAM_SIZE * 1024 * 1024;
  80 }
  81
  82 int testdram(void)
  83 {
  84         /* TODO: XXX XXX XXX */
  85         printf("DRAM test not implemented!\n");
  86
  87         return (0);
  88 }
  89
  90 #ifdef CONFIG_CMD_IDE
  91 #include <ata.h>
  92 int ide_preinit(void)
  93 {
  94         return (0);
  95 }
  96
  97 void ide_set_reset(int idereset)
  98 {
  99         volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
 100         long period;
 101         /*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 102         int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},       /* PIO 0 */
 103         {50, 125, 45, 20, 35, 5, 15, 0, 35},    /* PIO 1 */
 104         {30, 100, 30, 15, 20, 5, 10, 0, 35},    /* PIO 2 */
 105         {30, 80, 30, 10, 20, 5, 10, 0, 35},     /* PIO 3 */
 106         {25, 70, 20, 10, 20, 5, 10, 0, 35}      /* PIO 4 */
 107         };
 108
 109         if (idereset) {
 110                 ata->cr = 0;    /* control reset */
 111                 udelay(100);
 112         } else {
 113                 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 114
 115 #define CALC_TIMING(t) (t + period - 1) / period
 116                 period = 1000000000 / (CFG_CLK / 2);    /* period in ns */
 117
 118                 /*ata->ton = CALC_TIMING (180); */
 119                 ata->t1 = CALC_TIMING(piotms[2][0]);
 120                 ata->t2w = CALC_TIMING(piotms[2][1]);
 121                 ata->t2r = CALC_TIMING(piotms[2][1]);
 122                 ata->ta = CALC_TIMING(piotms[2][8]);
 123                 ata->trd = CALC_TIMING(piotms[2][7]);
 124                 ata->t4 = CALC_TIMING(piotms[2][3]);
 125                 ata->t9 = CALC_TIMING(piotms[2][6]);
 126
 127                 ata->cr = 0x40; /* IORDY enable */
 128                 udelay(2000);
 129                 ata->cr |= 0x01;        /* IORDY enable */
 130         }
 131 }
 132 #endif                          /* CONFIG_CMD_IDE */