board/freescale/m5275evb/m5275evb.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
   6  *
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/immap.h>
  14 #include <asm/io.h>
  15
  16 #define PERIOD          13      /* system bus period in ns */
  17 #define SDRAM_TREFI     7800    /* in ns */
  18
  19 int checkboard(void)
  20 {
  21         puts("Board: ");
  22         puts("Freescale MCF5275 EVB\n");
  23         return 0;
  24 };
  25
  26 phys_size_t initdram(int board_type)
  27 {
  28         sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
  29         gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
  30
  31         /* Enable SDRAM */
  32         out_be16(&gpio_reg->par_sdram, 0x3FF);
  33
  34         /* Set up chip select */
  35         out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
  36         out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
  37
  38         /* Set up timing */
  39         out_be32(&sdp->sdcfg1, 0x83711630);
  40         out_be32(&sdp->sdcfg2, 0x46770000);
  41
  42         /* Enable clock */
  43         out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
  44
  45         /* Set precharge */
  46         setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  47
  48         /* Dummy write to start SDRAM */
  49         *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  50
  51         /* Send LEMR */
  52         setbits_be32(&sdp->sdmr,
  53                 MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
  54                 MCF_SDRAMC_SDMR_CMD);
  55         *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  56
  57         /* Send LMR */
  58         out_be32(&sdp->sdmr, 0x058d0000);
  59         *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  60
  61         /* Stop sending commands */
  62         clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
  63
  64         /* Set precharge */
  65         setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  66         *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  67
  68         /* Stop manual precharge, send 2 IREF */
  69         clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  70         setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
  71         *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  72         *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  73
  74
  75         out_be32(&sdp->sdmr, 0x018d0000);
  76         *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  77
  78         /* Stop sending commands */
  79         clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
  80         clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
  81
  82         /* Turn on auto refresh, lock SDMR */
  83         out_be32(&sdp->sdcr,
  84                 MCF_SDRAMC_SDCR_CKE
  85                 | MCF_SDRAMC_SDCR_REF
  86                 | MCF_SDRAMC_SDCR_MUX(1)
  87                 /* 1 added to round up */
  88                 | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
  89                 | MCF_SDRAMC_SDCR_DQS_OE(0x3));
  90
  91         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  92 };
  93
  94 int testdram(void)
  95 {
  96         /* TODO: XXX XXX XXX */
  97         printf("DRAM test not implemented!\n");
  98
  99         return (0);
 100 }