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git.ipfire.org Git - people/ms/u-boot.git/blob - board/freescale/m5275evb/mii.c
706d8d6b24e07240e8903ce7988f050a2dde5ea6
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/immap.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
37 int fecpin_setclear(struct eth_device
*dev
, int setclear
)
39 struct fec_info_s
*info
= (struct fec_info_s
*) dev
->priv
;
40 volatile gpio_t
*gpio
= (gpio_t
*)MMAP_GPIO
;
43 /* Enable Ethernet pins */
44 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
) {
45 gpio
->par_feci2c
|= 0x0F00;
46 gpio
->par_fec0hl
|= 0xC0;
48 gpio
->par_feci2c
|= 0x00A0;
49 gpio
->par_fec1hl
|= 0xC0;
52 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
) {
53 gpio
->par_feci2c
&= ~0x0F00;
54 gpio
->par_fec0hl
&= ~0xC0;
56 gpio
->par_feci2c
&= ~0x00A0;
57 gpio
->par_fec1hl
&= ~0xC0;
64 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
67 /* Make MII read/write commands for the FEC. */
68 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
70 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
72 /* PHY identification */
73 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
74 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
75 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
76 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
77 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
78 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
79 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
80 #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
81 #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
82 #define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
84 #define STR_ID_LXT970 "LXT970"
85 #define STR_ID_LXT971 "LXT971"
86 #define STR_ID_82555 "Intel82555"
87 #define STR_ID_QS6612 "QS6612"
88 #define STR_ID_AMD79C784 "AMD79C784"
89 #define STR_ID_LSI80225 "LSI80225"
90 #define STR_ID_LSI80225B "LSI80225/B"
91 #define STR_ID_DP83848VV "N83848"
92 #define STR_ID_DP83849 "N83849"
93 #define STR_ID_KS8721BL "KS8721BL"
95 /****************************************************************************
96 * mii_init -- Initialize the MII for MII command without ethernet
97 * This function is a subset of eth_init
98 ****************************************************************************
100 void mii_reset(struct fec_info_s
*info
)
102 volatile fec_t
*fecp
= (fec_t
*) (info
->miibase
);
105 fecp
->ecr
= FEC_ECR_RESET
;
106 for (i
= 0; (fecp
->ecr
& FEC_ECR_RESET
) && (i
< FEC_RESET_DELAY
); ++i
) {
109 if (i
== FEC_RESET_DELAY
) {
110 printf("FEC_RESET_DELAY timeout\n");
114 /* send command to phy using mii, wait for result */
115 uint
mii_send(uint mii_cmd
)
117 struct fec_info_s
*info
;
118 struct eth_device
*dev
;
123 /* retrieve from register structure */
127 ep
= (fec_t
*) info
->miibase
;
129 ep
->mmfr
= mii_cmd
; /* command to phy */
131 /* wait for mii complete */
132 while (!(ep
->eir
& FEC_EIR_MII
) && (j
< MCFFEC_TOUT_LOOP
)) {
136 if (j
>= MCFFEC_TOUT_LOOP
) {
137 printf("MII not complete\n");
141 mii_reply
= ep
->mmfr
; /* result from phy */
142 ep
->eir
= FEC_EIR_MII
; /* clear MII complete */
144 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
145 __FILE__
, __LINE__
, __FUNCTION__
, mii_cmd
, mii_reply
);
148 return (mii_reply
& 0xffff); /* data read from phy */
150 #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
152 #if defined(CONFIG_SYS_DISCOVER_PHY)
153 int mii_discover_phy(struct eth_device
*dev
)
155 #define MAX_PHY_PASSES 11
156 struct fec_info_s
*info
= dev
->priv
;
160 if (info
->phyname_init
)
161 return info
->phy_addr
;
163 phyaddr
= -1; /* didn't find a PHY yet */
164 for (pass
= 1; pass
<= MAX_PHY_PASSES
&& phyaddr
< 0; ++pass
) {
166 /* PHY may need more time to recover from reset.
167 * The LXT970 needs 50ms typical, no maximum is
168 * specified, so wait 10ms before try again.
169 * With 11 passes this gives it 100ms to wake up.
171 udelay(10000); /* wait 10ms */
174 for (phyno
= 0; phyno
< 32 && phyaddr
< 0; ++phyno
) {
176 phytype
= mii_send(mk_mii_read(phyno
, PHY_PHYIDR1
));
178 printf("PHY type 0x%x pass %d type\n", phytype
, pass
);
180 if (phytype
!= 0xffff) {
184 mii_send(mk_mii_read(phyno
, PHY_PHYIDR2
));
186 switch (phytype
& 0xffffffff) {
187 case PHY_ID_KS8721BL
:
188 strcpy(info
->phy_name
,
190 info
->phyname_init
= 1;
193 strcpy(info
->phy_name
, "unknown");
194 info
->phyname_init
= 1;
199 printf("PHY @ 0x%x pass %d type ", phyno
, pass
);
200 switch (phytype
& 0xffffffff) {
201 case PHY_ID_KS8721BL
:
202 printf(STR_ID_KS8721BL
);
205 printf("0x%08x\n", phytype
);
213 printf("No PHY device found.\n");
217 #endif /* CONFIG_SYS_DISCOVER_PHY */
219 void mii_init(void) __attribute__((weak
,alias("__mii_init")));
221 void __mii_init(void)
223 volatile fec_t
*fecp
;
224 struct fec_info_s
*info
;
225 struct eth_device
*dev
;
226 int miispd
= 0, i
= 0;
229 /* retrieve from register structure */
233 fecp
= (fec_t
*) info
->miibase
;
235 fecpin_setclear(dev
, 1);
239 /* We use strictly polling mode only */
242 /* Clear any pending interrupt */
243 fecp
->eir
= 0xffffffff;
246 miispd
= (gd
->bus_clk
/ 1000000) / 5;
247 fecp
->mscr
= miispd
<< 1;
249 info
->phy_addr
= mii_discover_phy(dev
);
251 #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
252 while (i
< MCFFEC_TOUT_LOOP
) {
254 miiphy_read(dev
->name
, info
->phy_addr
, PHY_BMSR
, &autoneg
);
257 if ((autoneg
& AUTONEGLINK
) == AUTONEGLINK
)
262 if (i
>= MCFFEC_TOUT_LOOP
) {
263 printf("Auto Negotiation not complete\n");
266 /* adapt to the half/full speed settings */
267 info
->dup_spd
= miiphy_duplex(dev
->name
, info
->phy_addr
) << 16;
268 info
->dup_spd
|= miiphy_speed(dev
->name
, info
->phy_addr
);
271 /*****************************************************************************
272 * Read and write a MII PHY register, routines used by MII Utilities
274 * FIXME: These routines are expected to return 0 on success, but mii_send
275 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
276 * no PHY connected...
277 * For now always return 0.
278 * FIXME: These routines only work after calling eth_init() at least once!
279 * Otherwise they hang in mii_send() !!! Sorry!
280 *****************************************************************************/
282 int mcffec_miiphy_read(char *devname
, unsigned char addr
, unsigned char reg
,
283 unsigned short *value
)
285 short rdreg
; /* register working value */
288 printf("miiphy_read(0x%x) @ 0x%x = ", reg
, addr
);
290 rdreg
= mii_send(mk_mii_read(addr
, reg
));
295 printf("0x%04x\n", *value
);
301 int mcffec_miiphy_write(char *devname
, unsigned char addr
, unsigned char reg
,
302 unsigned short value
)
304 short rdreg
; /* register working value */
307 printf("miiphy_write(0x%x) @ 0x%x = ", reg
, addr
);
310 rdreg
= mii_send(mk_mii_write(addr
, reg
, value
));
313 printf("0x%04x\n", value
);
319 #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */