2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/immap.h>
16 DECLARE_GLOBAL_DATA_PTR
;
21 puts("Freescale M54455 EVB\n");
30 * Serial Boot: The dram is already initialized in start.S
31 * only require to return DRAM size
33 dramsize
= CONFIG_SYS_SDRAM_SIZE
* 0x100000 >> 1;
35 sdramc_t
*sdram
= (sdramc_t
*)(MMAP_SDRAM
);
36 gpio_t
*gpio
= (gpio_t
*)(MMAP_GPIO
);
39 dramsize
= CONFIG_SYS_SDRAM_SIZE
* 0x100000 >> 1;
41 for (i
= 0x13; i
< 0x20; i
++) {
42 if (dramsize
== (1 << i
))
47 out_8(&gpio
->mscr_sdram
, CONFIG_SYS_SDRAM_DRV_STRENGTH
);
49 out_be32(&sdram
->sdcs0
, CONFIG_SYS_SDRAM_BASE
| i
);
50 out_be32(&sdram
->sdcs1
, CONFIG_SYS_SDRAM_BASE1
| i
);
52 out_be32(&sdram
->sdcfg1
, CONFIG_SYS_SDRAM_CFG1
);
53 out_be32(&sdram
->sdcfg2
, CONFIG_SYS_SDRAM_CFG2
);
56 out_be32(&sdram
->sdcr
, CONFIG_SYS_SDRAM_CTRL
| 2);
59 out_be32(&sdram
->sdmr
, CONFIG_SYS_SDRAM_EMOD
| 0x408);
60 out_be32(&sdram
->sdmr
, CONFIG_SYS_SDRAM_MODE
| 0x300);
65 out_be32(&sdram
->sdcr
, CONFIG_SYS_SDRAM_CTRL
| 2);
67 /* Perform two refresh cycles */
68 out_be32(&sdram
->sdcr
, CONFIG_SYS_SDRAM_CTRL
| 4);
69 out_be32(&sdram
->sdcr
, CONFIG_SYS_SDRAM_CTRL
| 4);
71 out_be32(&sdram
->sdmr
, CONFIG_SYS_SDRAM_MODE
| 0x200);
73 out_be32(&sdram
->sdcr
,
74 (CONFIG_SYS_SDRAM_CTRL
& ~0x80000000) | 0x10000c00);
78 gd
->ram_size
= dramsize
<< 1;
85 /* TODO: XXX XXX XXX */
86 printf("DRAM test not implemented!\n");
91 #if defined(CONFIG_IDE)
96 gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
99 tmp
= (in_8(&gpio
->par_fec
) & GPIO_PAR_FEC_FEC1_UNMASK
) | 0x10;
100 setbits_8(&gpio
->par_fec
, tmp
);
101 tmp
= ((in_be16(&gpio
->par_feci2c
) & 0xf0ff) |
102 (GPIO_PAR_FECI2C_MDC1_ATA_DIOR
| GPIO_PAR_FECI2C_MDIO1_ATA_DIOW
));
103 setbits_be16(&gpio
->par_feci2c
, tmp
);
105 setbits_be16(&gpio
->par_ata
,
106 GPIO_PAR_ATA_BUFEN
| GPIO_PAR_ATA_CS1
| GPIO_PAR_ATA_CS0
|
107 GPIO_PAR_ATA_DA2
| GPIO_PAR_ATA_DA1
| GPIO_PAR_ATA_DA0
|
108 GPIO_PAR_ATA_RESET_RESET
| GPIO_PAR_ATA_DMARQ_DMARQ
|
109 GPIO_PAR_ATA_IORDY_IORDY
);
110 setbits_be16(&gpio
->par_pci
,
111 GPIO_PAR_PCI_GNT3_ATA_DMACK
| GPIO_PAR_PCI_REQ3_ATA_INTRQ
);
116 void ide_set_reset(int idereset
)
118 atac_t
*ata
= (atac_t
*) MMAP_ATA
;
120 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
122 {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
123 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
124 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
125 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
126 {25, 70, 20, 10, 20, 5, 10, 0, 35}
134 #define CALC_TIMING(t) (t + period - 1) / period
135 period
= 1000000000 / gd
->bus_clk
; /* period in ns */
137 /*ata->ton = CALC_TIMING (180); */
138 out_8(&ata
->t1
, CALC_TIMING(piotms
[2][0]));
139 out_8(&ata
->t2w
, CALC_TIMING(piotms
[2][1]));
140 out_8(&ata
->t2r
, CALC_TIMING(piotms
[2][1]));
141 out_8(&ata
->ta
, CALC_TIMING(piotms
[2][8]));
142 out_8(&ata
->trd
, CALC_TIMING(piotms
[2][7]));
143 out_8(&ata
->t4
, CALC_TIMING(piotms
[2][3]));
144 out_8(&ata
->t9
, CALC_TIMING(piotms
[2][6]));
147 out_8(&ata
->cr
, 0x40);
150 setbits_8(&ata
->cr
, 0x01);
155 #if defined(CONFIG_PCI)
157 * Initialize PCI devices, report devices found.
159 static struct pci_controller hose
;
160 extern void pci_mcf5445x_init(struct pci_controller
*hose
);
162 void pci_init_board(void)
164 pci_mcf5445x_init(&hose
);
166 #endif /* CONFIG_PCI */
168 #if defined(CONFIG_FLASH_CFI_LEGACY)
170 ulong
board_flash_get_legacy (ulong base
, int banknum
, flash_info_t
* info
)
172 int sect
[] = CONFIG_SYS_ATMEL_SECT
;
173 int sectsz
[] = CONFIG_SYS_ATMEL_SECTSZ
;
176 if (base
!= CONFIG_SYS_ATMEL_BASE
)
179 info
->flash_id
= 0x01000000;
182 info
->buffer_size
= 1;
183 info
->erase_blk_tout
= 16384;
184 info
->write_tout
= 2;
185 info
->buffer_write_tout
= 5;
186 info
->vendor
= 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
187 info
->cmd_reset
= 0x00F0;
188 info
->interface
= FLASH_CFI_X8
;
189 info
->legacy_unlock
= 0;
190 info
->manufacturer_id
= (u16
) ATM_MANUFACT
;
191 info
->device_id
= ATM_ID_LV040
;
192 info
->device_id2
= 0;
195 info
->cfi_version
= 0x3133;
196 info
->cfi_offset
= 0x0000;
197 info
->addr_unlock1
= 0x00000555;
198 info
->addr_unlock2
= 0x000002AA;
199 info
->name
= "CFI conformant";
202 info
->sector_count
= CONFIG_SYS_ATMEL_TOTALSECT
;
203 info
->start
[0] = base
;
204 for (k
= 0, i
= 0; i
< CONFIG_SYS_ATMEL_REGION
; i
++) {
205 info
->size
+= sect
[i
] * sectsz
[i
];
207 for (j
= 0; j
< sect
[i
]; j
++, k
++) {
208 info
->start
[k
+ 1] = info
->start
[k
] + sectsz
[i
];
209 info
->protect
[k
] = 0;
215 #endif /* CONFIG_SYS_FLASH_CFI */