board/freescale/mpc5121ads/mpc5121ads.c

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <common.h>
  25 #include <asm/bitops.h>
  26 #include <command.h>
  27 #include <asm/io.h>
  28 #include <asm/processor.h>
  29 #include <asm/mpc512x.h>
  30 #include <fdt_support.h>
  31 #ifdef CONFIG_MISC_INIT_R
  32 #include <i2c.h>
  33 #endif
  34
  35 #include <linux/mtd/mtd.h>
  36 #include <linux/mtd/nand.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 /* Clocks in use */
  41 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
  42                          CLOCK_SCCR1_DDR_EN |                           \
  43                          CLOCK_SCCR1_FEC_EN |                           \
  44                          CLOCK_SCCR1_LPC_EN |                           \
  45                          CLOCK_SCCR1_NFC_EN |                           \
  46                          CLOCK_SCCR1_PATA_EN |                          \
  47                          CLOCK_SCCR1_PCI_EN |                           \
  48                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
  49                          CLOCK_SCCR1_PSCFIFO_EN |                       \
  50                          CLOCK_SCCR1_TPR_EN)
  51
  52 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN |           \
  53                          CLOCK_SCCR2_I2C_EN |           \
  54                          CLOCK_SCCR2_MEM_EN |           \
  55                          CLOCK_SCCR2_SPDIF_EN)
  56
  57 void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
  58
  59 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
  60 extern int mpc5121_nfc_chip;
  61
  62 /* Control chips select signal on MPC5121ADS board */
  63 void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
  64 {
  65         unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
  66         u8 v;
  67
  68         v = in_8(csreg);
  69         v |= 0x0F;
  70
  71         if (chip >= 0) {
  72                 __mpc5121_nfc_select_chip(mtd, 0);
  73                 v &= ~(1 << mpc5121_nfc_chip);
  74         } else {
  75                 __mpc5121_nfc_select_chip(mtd, -1);
  76         }
  77
  78         out_8(csreg, v);
  79 }
  80
  81 int board_early_init_f(void)
  82 {
  83         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  84         u32 spridr;
  85
  86         /*
  87          * Initialize Local Window for the CPLD registers access (CS2 selects
  88          * the CPLD chip)
  89          */
  90         out_be32(&im->sysconf.lpcs2aw,
  91                 CSAW_START(CONFIG_SYS_CPLD_BASE) |
  92                 CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
  93         );
  94         out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
  95         sync_law(&im->sysconf.lpcs2aw);
  96
  97         /*
  98          * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
  99          *
 100          * Without this the flash identification routine fails, as it needs to issue
 101          * write commands in order to establish the device ID.
 102          */
 103
 104 #ifdef CONFIG_ADS5121_REV2
 105         out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
 106 #else
 107         if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
 108                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
 109         } else {
 110                 /* running from Backup flash */
 111                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
 112         }
 113 #endif
 114         /*
 115          * Configure Flash Speed
 116          */
 117         out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
 118
 119         spridr = in_be32(&im->sysconf.spridr);
 120
 121         if (SVR_MJREV (spridr) >= 2)
 122                 out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
 123
 124         /*
 125          * Enable clocks
 126          */
 127         out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
 128         out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
 129 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
 130         setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
 131 #endif
 132
 133         return 0;
 134 }
 135
 136 phys_size_t initdram(int board_type)
 137 {
 138         u32 msize = 0;
 139
 140         msize = fixed_sdram(NULL, NULL, 0);
 141
 142         return msize;
 143 }
 144
 145 int misc_init_r(void)
 146 {
 147         u8 tmp_val;
 148
 149         /* Using this for DIU init before the driver in linux takes over
 150          *  Enable the TFP410 Encoder (I2C address 0x38)
 151          */
 152
 153         i2c_set_bus_num(2);
 154         tmp_val = 0xBF;
 155         i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 156         /* Verify if enabled */
 157         tmp_val = 0;
 158         i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 159         debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
 160
 161         tmp_val = 0x10;
 162         i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 163         /* Verify if enabled */
 164         tmp_val = 0;
 165         i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 166         debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
 167
 168 #ifdef CONFIG_FSL_DIU_FB
 169 # if    !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
 170         mpc5121_diu_init();
 171 # endif
 172 #endif
 173         return 0;
 174 }
 175
 176 static  iopin_t ioregs_init[] = {
 177         /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
 178         {
 179                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
 180                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 181                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 182         },
 183         /* Set highest Slew on 9 PATA pins */
 184         {
 185                 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
 186                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 187                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 188         },
 189         /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
 190         {
 191                 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
 192                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 193                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 194         },
 195         /* FUNC1=SPDIF_TXCLK */
 196         {
 197                 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
 198                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 199                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 200         },
 201         /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
 202         {
 203                 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
 204                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 205                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 206         },
 207         /* FUNC2=DIU CLK */
 208         {
 209                 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
 210                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 211                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 212         },
 213         /* FUNC2=DIU_HSYNC */
 214         {
 215                 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
 216                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 217                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 218         },
 219         /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
 220         {
 221                 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
 222                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 223                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 224         }
 225 };
 226
 227 static  iopin_t rev2_silicon_pci_ioregs_init[] = {
 228         /* FUNC0=PCI Sets next 54 to PCI pads */
 229         {
 230                 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
 231                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
 232         }
 233 };
 234
 235 int checkboard (void)
 236 {
 237         ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
 238         uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 239         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 240         u32 spridr = in_be32(&im->sysconf.spridr);
 241
 242         printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 243                 brd_rev, cpld_rev);
 244
 245         /* initialize function mux & slew rate IO inter alia on IO Pins  */
 246         iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 247
 248         if (SVR_MJREV (spridr) >= 2)
 249                 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
 250
 251         return 0;
 252 }
 253
 254 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 255 void ft_board_setup(void *blob, bd_t *bd)
 256 {
 257         ft_cpu_setup(blob, bd);
 258         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 259 }
 260 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */