board/freescale/mpc5121ads/mpc5121ads.c

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <common.h>
  25 #include <asm/bitops.h>
  26 #include <command.h>
  27 #include <asm/io.h>
  28 #include <asm/processor.h>
  29 #include <asm/mpc512x.h>
  30 #include <fdt_support.h>
  31 #ifdef CONFIG_MISC_INIT_R
  32 #include <i2c.h>
  33 #endif
  34 #include <net.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
  42
  43 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
  44 extern int mpc5121_nfc_chip;
  45
  46 /* Control chips select signal on MPC5121ADS board */
  47 void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
  48 {
  49         unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
  50         u8 v;
  51
  52         v = in_8(csreg);
  53         v |= 0x0F;
  54
  55         if (chip >= 0) {
  56                 __mpc5121_nfc_select_chip(mtd, 0);
  57                 v &= ~(1 << mpc5121_nfc_chip);
  58         } else {
  59                 __mpc5121_nfc_select_chip(mtd, -1);
  60         }
  61
  62         out_8(csreg, v);
  63 }
  64
  65 int board_early_init_f(void)
  66 {
  67         /*
  68          * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
  69          *
  70          * Without this the flash identification routine fails, as it needs to issue
  71          * write commands in order to establish the device ID.
  72          */
  73
  74 #ifdef CONFIG_MPC5121ADS_REV2
  75         out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
  76 #else
  77         if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
  78                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
  79         } else {
  80                 /* running from Backup flash */
  81                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
  82         }
  83 #endif
  84         return 0;
  85 }
  86
  87 int is_micron(void){
  88
  89         ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
  90         uchar macaddr[6];
  91         u32 brddate, macchk, ismicron;
  92
  93         /*
  94          * MAC address has serial number with date of manufacture
  95          * Boards made before Nov-08 #1180 use Micron memory;
  96          * 001e59 is the STx vendor #
  97          * Default is Elpida since it works for both but is slightly slower
  98          */
  99         ismicron = 0;
 100         if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
 101                 brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
 102                 macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
 103                 debug("brddate = %d\n\t", brddate);
 104
 105                 if (macchk == 0x001e59 && brddate <= 8111180)
 106                         ismicron = 1;
 107         } else if (brd_rev < 0x400) {
 108                 ismicron = 1;
 109         }
 110         debug("Using %s Memory settings\n\t",
 111                 ismicron ? "Micron" : "Elpida");
 112         return(ismicron);
 113 }
 114
 115 phys_size_t initdram(int board_type)
 116 {
 117         u32 msize = 0;
 118         /*
 119          * Elpida MDDRC and initialization settings are an alternative
 120          * to the Default Micron ones for all but the earliest Rev 4 boards
 121          */
 122         ddr512x_config_t elpida_mddrc_config = {
 123                 .ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
 124                 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
 125                 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
 126                 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
 127         };
 128
 129         u32 elpida_init_sequence[] = {
 130                 CONFIG_SYS_DDRCMD_NOP,
 131                 CONFIG_SYS_DDRCMD_NOP,
 132                 CONFIG_SYS_DDRCMD_NOP,
 133                 CONFIG_SYS_DDRCMD_NOP,
 134                 CONFIG_SYS_DDRCMD_NOP,
 135                 CONFIG_SYS_DDRCMD_NOP,
 136                 CONFIG_SYS_DDRCMD_NOP,
 137                 CONFIG_SYS_DDRCMD_NOP,
 138                 CONFIG_SYS_DDRCMD_NOP,
 139                 CONFIG_SYS_DDRCMD_NOP,
 140                 CONFIG_SYS_DDRCMD_PCHG_ALL,
 141                 CONFIG_SYS_DDRCMD_NOP,
 142                 CONFIG_SYS_DDRCMD_RFSH,
 143                 CONFIG_SYS_DDRCMD_NOP,
 144                 CONFIG_SYS_DDRCMD_RFSH,
 145                 CONFIG_SYS_DDRCMD_NOP,
 146                 CONFIG_SYS_DDRCMD_EM2,
 147                 CONFIG_SYS_DDRCMD_EM3,
 148                 CONFIG_SYS_DDRCMD_EN_DLL,
 149                 CONFIG_SYS_ELPIDA_RES_DLL,
 150                 CONFIG_SYS_DDRCMD_PCHG_ALL,
 151                 CONFIG_SYS_DDRCMD_RFSH,
 152                 CONFIG_SYS_DDRCMD_RFSH,
 153                 CONFIG_SYS_DDRCMD_RFSH,
 154                 CONFIG_SYS_ELPIDA_INIT_DEV_OP,
 155                 CONFIG_SYS_DDRCMD_NOP,
 156                 CONFIG_SYS_DDRCMD_NOP,
 157                 CONFIG_SYS_DDRCMD_NOP,
 158                 CONFIG_SYS_DDRCMD_NOP,
 159                 CONFIG_SYS_DDRCMD_NOP,
 160                 CONFIG_SYS_DDRCMD_NOP,
 161                 CONFIG_SYS_DDRCMD_NOP,
 162                 CONFIG_SYS_DDRCMD_NOP,
 163                 CONFIG_SYS_DDRCMD_NOP,
 164                 CONFIG_SYS_DDRCMD_NOP,
 165                 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
 166                 CONFIG_SYS_ELPIDA_OCD_EXIT,
 167                 CONFIG_SYS_DDRCMD_NOP,
 168                 CONFIG_SYS_DDRCMD_NOP,
 169                 CONFIG_SYS_DDRCMD_NOP,
 170                 CONFIG_SYS_DDRCMD_NOP,
 171                 CONFIG_SYS_DDRCMD_NOP,
 172                 CONFIG_SYS_DDRCMD_NOP,
 173                 CONFIG_SYS_DDRCMD_NOP,
 174                 CONFIG_SYS_DDRCMD_NOP,
 175                 CONFIG_SYS_DDRCMD_NOP,
 176                 CONFIG_SYS_DDRCMD_NOP
 177         };
 178
 179         if (is_micron()) {
 180                 msize = fixed_sdram(NULL, NULL, 0);
 181         } else {
 182                 msize = fixed_sdram(&elpida_mddrc_config,
 183                                 elpida_init_sequence,
 184                                 sizeof(elpida_init_sequence)/sizeof(u32));
 185         }
 186
 187         return msize;
 188 }
 189
 190 int misc_init_r(void)
 191 {
 192         u8 tmp_val;
 193
 194         /* Using this for DIU init before the driver in linux takes over
 195          *  Enable the TFP410 Encoder (I2C address 0x38)
 196          */
 197
 198         i2c_set_bus_num(2);
 199         tmp_val = 0xBF;
 200         i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 201         /* Verify if enabled */
 202         tmp_val = 0;
 203         i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 204         debug("DVI Encoder Read: 0x%02x\n", tmp_val);
 205
 206         tmp_val = 0x10;
 207         i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 208         /* Verify if enabled */
 209         tmp_val = 0;
 210         i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 211         debug("DVI Encoder Read: 0x%02x\n", tmp_val);
 212
 213         return 0;
 214 }
 215
 216 static  iopin_t ioregs_init[] = {
 217         /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
 218         {
 219                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
 220                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 221                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 222         },
 223         /* Set highest Slew on 9 PATA pins */
 224         {
 225                 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
 226                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 227                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 228         },
 229         /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
 230         {
 231                 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
 232                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 233                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 234         },
 235         /* FUNC1=SPDIF_TXCLK */
 236         {
 237                 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
 238                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 239                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 240         },
 241         /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
 242         {
 243                 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
 244                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 245                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 246         },
 247         /* FUNC2=DIU CLK */
 248         {
 249                 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
 250                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 251                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 252         },
 253         /* FUNC2=DIU_HSYNC */
 254         {
 255                 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
 256                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 257                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 258         },
 259         /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
 260         {
 261                 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
 262                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 263                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 264         }
 265 };
 266
 267 static  iopin_t rev2_silicon_pci_ioregs_init[] = {
 268         /* FUNC0=PCI Sets next 54 to PCI pads */
 269         {
 270                 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
 271                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
 272         }
 273 };
 274
 275 int checkboard (void)
 276 {
 277         ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
 278         uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 279         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 280         u32 spridr = in_be32(&im->sysconf.spridr);
 281
 282         printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
 283                 brd_rev, cpld_rev);
 284
 285         /* initialize function mux & slew rate IO inter alia on IO Pins  */
 286         iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 287
 288         if (SVR_MJREV (spridr) >= 2)
 289                 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
 290
 291         return 0;
 292 }
 293
 294 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 295 void ft_board_setup(void *blob, bd_t *bd)
 296 {
 297         ft_cpu_setup(blob, bd);
 298 }
 299 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */