board/freescale/mpc5121ads/mpc5121ads.c

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <common.h>
  25 #include <asm/bitops.h>
  26 #include <command.h>
  27 #include <asm/io.h>
  28 #include <asm/processor.h>
  29 #include <asm/mpc512x.h>
  30 #include <fdt_support.h>
  31 #ifdef CONFIG_MISC_INIT_R
  32 #include <i2c.h>
  33 #endif
  34 #include <net.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 /* Clocks in use */
  42 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
  43                          CLOCK_SCCR1_DDR_EN |                           \
  44                          CLOCK_SCCR1_FEC_EN |                           \
  45                          CLOCK_SCCR1_LPC_EN |                           \
  46                          CLOCK_SCCR1_NFC_EN |                           \
  47                          CLOCK_SCCR1_PATA_EN |                          \
  48                          CLOCK_SCCR1_PCI_EN |                           \
  49                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
  50                          CLOCK_SCCR1_PSCFIFO_EN |                       \
  51                          CLOCK_SCCR1_TPR_EN)
  52
  53 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN |           \
  54                          CLOCK_SCCR2_I2C_EN |           \
  55                          CLOCK_SCCR2_MEM_EN |           \
  56                          CLOCK_SCCR2_SPDIF_EN)
  57
  58 void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
  59
  60 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
  61 extern int mpc5121_nfc_chip;
  62
  63 /* Control chips select signal on MPC5121ADS board */
  64 void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
  65 {
  66         unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
  67         u8 v;
  68
  69         v = in_8(csreg);
  70         v |= 0x0F;
  71
  72         if (chip >= 0) {
  73                 __mpc5121_nfc_select_chip(mtd, 0);
  74                 v &= ~(1 << mpc5121_nfc_chip);
  75         } else {
  76                 __mpc5121_nfc_select_chip(mtd, -1);
  77         }
  78
  79         out_8(csreg, v);
  80 }
  81
  82 int board_early_init_f(void)
  83 {
  84         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  85         u32 spridr;
  86
  87         /*
  88          * Initialize Local Window for the CPLD registers access (CS2 selects
  89          * the CPLD chip)
  90          */
  91         out_be32(&im->sysconf.lpcs2aw,
  92                 CSAW_START(CONFIG_SYS_CPLD_BASE) |
  93                 CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
  94         );
  95         out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
  96         sync_law(&im->sysconf.lpcs2aw);
  97
  98         /*
  99          * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
 100          *
 101          * Without this the flash identification routine fails, as it needs to issue
 102          * write commands in order to establish the device ID.
 103          */
 104
 105 #ifdef CONFIG_ADS5121_REV2
 106         out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
 107 #else
 108         if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
 109                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
 110         } else {
 111                 /* running from Backup flash */
 112                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
 113         }
 114 #endif
 115         /*
 116          * Configure Flash Speed
 117          */
 118         out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
 119
 120         spridr = in_be32(&im->sysconf.spridr);
 121
 122         if (SVR_MJREV (spridr) >= 2)
 123                 out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
 124
 125         /*
 126          * Enable clocks
 127          */
 128         out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
 129         out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
 130 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
 131         setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
 132 #endif
 133
 134         return 0;
 135 }
 136
 137 int is_micron(void){
 138
 139         ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
 140         uchar macaddr[6];
 141         u32 brddate, macchk, ismicron;
 142
 143         /*
 144          * MAC address has serial number with date of manufacture
 145          * Boards made before Nov-08 #1180 use Micron memory;
 146          * 001e59 is the STx vendor #
 147          * Default is Elpida since it works for both but is slightly slower
 148          */
 149         ismicron = 0;
 150         if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
 151                 brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
 152                 macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
 153                 debug("brddate = %d\n\t", brddate);
 154
 155                 if (macchk == 0x001e59 && brddate <= 8111180)
 156                         ismicron = 1;
 157         } else if (brd_rev < 0x400) {
 158                 ismicron = 1;
 159         }
 160         debug("Using %s Memory settings\n\t",
 161                 ismicron ? "Micron" : "Elpida");
 162         return(ismicron);
 163 }
 164
 165 phys_size_t initdram(int board_type)
 166 {
 167         u32 msize = 0;
 168         /*
 169          * Elpida MDDRC and initialization settings are an alternative
 170          * to the Default Micron ones for all but the earliest Rev 4 boards
 171          */
 172         ddr512x_config_t elpida_mddrc_config = {
 173                 .ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
 174                 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
 175                 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
 176                 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
 177         };
 178
 179         u32 elpida_init_sequence[] = {
 180                 CONFIG_SYS_DDRCMD_NOP,
 181                 CONFIG_SYS_DDRCMD_NOP,
 182                 CONFIG_SYS_DDRCMD_NOP,
 183                 CONFIG_SYS_DDRCMD_NOP,
 184                 CONFIG_SYS_DDRCMD_NOP,
 185                 CONFIG_SYS_DDRCMD_NOP,
 186                 CONFIG_SYS_DDRCMD_NOP,
 187                 CONFIG_SYS_DDRCMD_NOP,
 188                 CONFIG_SYS_DDRCMD_NOP,
 189                 CONFIG_SYS_DDRCMD_NOP,
 190                 CONFIG_SYS_DDRCMD_PCHG_ALL,
 191                 CONFIG_SYS_DDRCMD_NOP,
 192                 CONFIG_SYS_DDRCMD_RFSH,
 193                 CONFIG_SYS_DDRCMD_NOP,
 194                 CONFIG_SYS_DDRCMD_RFSH,
 195                 CONFIG_SYS_DDRCMD_NOP,
 196                 CONFIG_SYS_DDRCMD_EM2,
 197                 CONFIG_SYS_DDRCMD_EM3,
 198                 CONFIG_SYS_DDRCMD_EN_DLL,
 199                 CONFIG_SYS_ELPIDA_RES_DLL,
 200                 CONFIG_SYS_DDRCMD_PCHG_ALL,
 201                 CONFIG_SYS_DDRCMD_RFSH,
 202                 CONFIG_SYS_DDRCMD_RFSH,
 203                 CONFIG_SYS_DDRCMD_RFSH,
 204                 CONFIG_SYS_ELPIDA_INIT_DEV_OP,
 205                 CONFIG_SYS_DDRCMD_NOP,
 206                 CONFIG_SYS_DDRCMD_NOP,
 207                 CONFIG_SYS_DDRCMD_NOP,
 208                 CONFIG_SYS_DDRCMD_NOP,
 209                 CONFIG_SYS_DDRCMD_NOP,
 210                 CONFIG_SYS_DDRCMD_NOP,
 211                 CONFIG_SYS_DDRCMD_NOP,
 212                 CONFIG_SYS_DDRCMD_NOP,
 213                 CONFIG_SYS_DDRCMD_NOP,
 214                 CONFIG_SYS_DDRCMD_NOP,
 215                 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
 216                 CONFIG_SYS_ELPIDA_OCD_EXIT,
 217                 CONFIG_SYS_DDRCMD_NOP,
 218                 CONFIG_SYS_DDRCMD_NOP,
 219                 CONFIG_SYS_DDRCMD_NOP,
 220                 CONFIG_SYS_DDRCMD_NOP,
 221                 CONFIG_SYS_DDRCMD_NOP,
 222                 CONFIG_SYS_DDRCMD_NOP,
 223                 CONFIG_SYS_DDRCMD_NOP,
 224                 CONFIG_SYS_DDRCMD_NOP,
 225                 CONFIG_SYS_DDRCMD_NOP,
 226                 CONFIG_SYS_DDRCMD_NOP
 227         };
 228
 229         if (is_micron()) {
 230                 msize = fixed_sdram(NULL, NULL, 0);
 231         } else {
 232                 msize = fixed_sdram(&elpida_mddrc_config,
 233                                 elpida_init_sequence,
 234                                 sizeof(elpida_init_sequence)/sizeof(u32));
 235         }
 236
 237         return msize;
 238 }
 239
 240 int misc_init_r(void)
 241 {
 242         u8 tmp_val;
 243
 244         /* Using this for DIU init before the driver in linux takes over
 245          *  Enable the TFP410 Encoder (I2C address 0x38)
 246          */
 247
 248         i2c_set_bus_num(2);
 249         tmp_val = 0xBF;
 250         i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 251         /* Verify if enabled */
 252         tmp_val = 0;
 253         i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 254         debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
 255
 256         tmp_val = 0x10;
 257         i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 258         /* Verify if enabled */
 259         tmp_val = 0;
 260         i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 261         debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
 262
 263         return 0;
 264 }
 265
 266 static  iopin_t ioregs_init[] = {
 267         /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
 268         {
 269                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
 270                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 271                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 272         },
 273         /* Set highest Slew on 9 PATA pins */
 274         {
 275                 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
 276                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 277                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 278         },
 279         /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
 280         {
 281                 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
 282                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 283                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 284         },
 285         /* FUNC1=SPDIF_TXCLK */
 286         {
 287                 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
 288                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 289                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 290         },
 291         /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
 292         {
 293                 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
 294                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 295                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 296         },
 297         /* FUNC2=DIU CLK */
 298         {
 299                 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
 300                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 301                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 302         },
 303         /* FUNC2=DIU_HSYNC */
 304         {
 305                 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
 306                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 307                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 308         },
 309         /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
 310         {
 311                 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
 312                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 313                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 314         }
 315 };
 316
 317 static  iopin_t rev2_silicon_pci_ioregs_init[] = {
 318         /* FUNC0=PCI Sets next 54 to PCI pads */
 319         {
 320                 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
 321                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
 322         }
 323 };
 324
 325 int checkboard (void)
 326 {
 327         ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
 328         uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 329         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 330         u32 spridr = in_be32(&im->sysconf.spridr);
 331
 332         printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 333                 brd_rev, cpld_rev);
 334
 335         /* initialize function mux & slew rate IO inter alia on IO Pins  */
 336         iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 337
 338         if (SVR_MJREV (spridr) >= 2)
 339                 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
 340
 341         return 0;
 342 }
 343
 344 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 345 void ft_board_setup(void *blob, bd_t *bd)
 346 {
 347         ft_cpu_setup(blob, bd);
 348 }
 349 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */