board/freescale/mpc8308rdb/mpc8308rdb.c

   1 /*
   2  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <hwconfig.h>
  10 #include <i2c.h>
  11 #include <spi.h>
  12 #include <libfdt.h>
  13 #include <fdt_support.h>
  14 #include <pci.h>
  15 #include <mpc83xx.h>
  16 #include <vsc7385.h>
  17 #include <netdev.h>
  18 #include <fsl_esdhc.h>
  19 #include <asm/io.h>
  20 #include <asm/fsl_serdes.h>
  21 #include <asm/fsl_mpc83xx_serdes.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /*
  26  * The following are used to control the SPI chip selects for the SPI command.
  27  */
  28 #ifdef CONFIG_MPC8XXX_SPI
  29
  30 #define SPI_CS_MASK     0x00400000
  31
  32 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  33 {
  34         return bus == 0 && cs == 0;
  35 }
  36
  37 void spi_cs_activate(struct spi_slave *slave)
  38 {
  39         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  40
  41         /* active low */
  42         clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  43 }
  44
  45 void spi_cs_deactivate(struct spi_slave *slave)
  46 {
  47         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  48
  49         /* inactive high */
  50         setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  51 }
  52 #endif /* CONFIG_MPC8XXX_SPI */
  53
  54 #ifdef CONFIG_FSL_ESDHC
  55 int board_mmc_init(bd_t *bd)
  56 {
  57         return fsl_esdhc_mmc_init(bd);
  58 }
  59 #endif
  60
  61 static u8 read_board_info(void)
  62 {
  63         u8 val8;
  64         i2c_set_bus_num(0);
  65
  66         if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
  67                 return val8;
  68         else
  69                 return 0;
  70 }
  71
  72 int checkboard(void)
  73 {
  74         static const char * const rev_str[] = {
  75                 "1.0",
  76                 "<reserved>",
  77                 "<reserved>",
  78                 "<reserved>",
  79                 "<unknown>",
  80         };
  81         u8 info;
  82         int i;
  83
  84         info = read_board_info();
  85         i = (!info) ? 4 : info & 0x03;
  86
  87         printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
  88
  89         return 0;
  90 }
  91
  92 static struct pci_region pcie_regions_0[] = {
  93         {
  94                 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  95                 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  96                 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  97                 .flags = PCI_REGION_MEM,
  98         },
  99         {
 100                 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
 101                 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
 102                 .size = CONFIG_SYS_PCIE1_IO_SIZE,
 103                 .flags = PCI_REGION_IO,
 104         },
 105 };
 106
 107 void pci_init_board(void)
 108 {
 109         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 110         sysconf83xx_t *sysconf = &immr->sysconf;
 111         law83xx_t *pcie_law = sysconf->pcielaw;
 112         struct pci_region *pcie_reg[] = { pcie_regions_0 };
 113
 114         fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
 115                                         FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 116
 117         /* Deassert the resets in the control register */
 118         out_be32(&sysconf->pecr1, 0xE0008000);
 119         udelay(2000);
 120
 121         /* Configure PCI Express Local Access Windows */
 122         out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
 123         out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
 124
 125         mpc83xx_pcie_init(1, pcie_reg);
 126 }
 127 /*
 128  * Miscellaneous late-boot configurations
 129  *
 130  * If a VSC7385 microcode image is present, then upload it.
 131 */
 132 int misc_init_r(void)
 133 {
 134 #ifdef CONFIG_MPC8XXX_SPI
 135         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 136         sysconf83xx_t *sysconf = &immr->sysconf;
 137
 138         /*
 139          * Set proper bits in SICRH to allow SPI on header J8
 140          *
 141          * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
 142          * switch. The pinmux configuration does not have a fine enough
 143          * granularity to support both simultaneously.
 144          */
 145         clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
 146         puts("WARNING: SPI enabled, TSEC2 support is broken\n");
 147
 148         /* Set header J8 SPI chip select output, disabled */
 149         setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
 150         setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
 151 #endif
 152
 153 #ifdef CONFIG_VSC7385_IMAGE
 154         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 155                 CONFIG_VSC7385_IMAGE_SIZE)) {
 156                 puts("Failure uploading VSC7385 microcode.\n");
 157                 return 1;
 158         }
 159 #endif
 160
 161         return 0;
 162 }
 163 #if defined(CONFIG_OF_BOARD_SETUP)
 164 void ft_board_setup(void *blob, bd_t *bd)
 165 {
 166         ft_cpu_setup(blob, bd);
 167         fdt_fixup_dr_usb(blob, bd);
 168         fdt_fixup_esdhc(blob, bd);
 169 }
 170 #endif
 171
 172 int board_eth_init(bd_t *bis)
 173 {
 174         int rv, num_if = 0;
 175
 176         /* Initialize TSECs first */
 177         rv = cpu_eth_init(bis);
 178         if (rv >= 0)
 179                 num_if += rv;
 180         else
 181                 printf("ERROR: failed to initialize TSECs.\n");
 182
 183         rv = pci_eth_init(bis);
 184         if (rv >= 0)
 185                 num_if += rv;
 186         else
 187                 printf("ERROR: failed to initialize PCI Ethernet.\n");
 188
 189         return num_if;
 190 }