2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
9 * This files is mostly identical to the original from
10 * board\freescale\mpc8315erdb\sdram.c
12 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/bitops.h>
21 #include <asm/processor.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 /* Fixed sdram init -- doesn't use serial presence detect.
27 * This is useful for faster booting in configs where the RAM is unlikely
28 * to be changed, or for things like NAND booting where space is tight.
30 static long fixed_sdram(void)
32 immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
33 u32 msize
= CONFIG_SYS_DDR_SIZE
* 1024 * 1024;
34 u32 msize_log2
= __ilog2(msize
);
36 out_be32(&im
->sysconf
.ddrlaw
[0].bar
,
37 CONFIG_SYS_DDR_SDRAM_BASE
& 0xfffff000);
38 out_be32(&im
->sysconf
.ddrlaw
[0].ar
, LBLAWAR_EN
| (msize_log2
- 1));
39 out_be32(&im
->sysconf
.ddrcdr
, CONFIG_SYS_DDRCDR_VALUE
);
41 out_be32(&im
->ddr
.csbnds
[0].csbnds
, (msize
- 1) >> 24);
42 out_be32(&im
->ddr
.cs_config
[0], CONFIG_SYS_DDR_CS0_CONFIG
);
44 /* Currently we use only one CS, so disable the other bank. */
45 out_be32(&im
->ddr
.cs_config
[1], 0);
47 out_be32(&im
->ddr
.sdram_clk_cntl
, CONFIG_SYS_DDR_SDRAM_CLK_CNTL
);
48 out_be32(&im
->ddr
.timing_cfg_3
, CONFIG_SYS_DDR_TIMING_3
);
49 out_be32(&im
->ddr
.timing_cfg_1
, CONFIG_SYS_DDR_TIMING_1
);
50 out_be32(&im
->ddr
.timing_cfg_2
, CONFIG_SYS_DDR_TIMING_2
);
51 out_be32(&im
->ddr
.timing_cfg_0
, CONFIG_SYS_DDR_TIMING_0
);
53 out_be32(&im
->ddr
.sdram_cfg
, CONFIG_SYS_DDR_SDRAM_CFG
);
54 out_be32(&im
->ddr
.sdram_cfg2
, CONFIG_SYS_DDR_SDRAM_CFG2
);
55 out_be32(&im
->ddr
.sdram_mode
, CONFIG_SYS_DDR_MODE
);
56 out_be32(&im
->ddr
.sdram_mode2
, CONFIG_SYS_DDR_MODE2
);
58 out_be32(&im
->ddr
.sdram_interval
, CONFIG_SYS_DDR_INTERVAL
);
61 /* enable DDR controller */
62 setbits_be32(&im
->ddr
.sdram_cfg
, SDRAM_CFG_MEM_EN
);
65 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE
, msize
);
68 phys_size_t
initdram(int board_type
)
70 immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
73 if ((in_be32(&im
->sysconf
.immrbar
) & IMMRBAR_BASE_ADDR
) != (u32
)im
)
77 msize
= fixed_sdram();
79 /* return total bus SDRAM size(bytes) -- DDR */