3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
32 #include <spd_sdram.h>
34 #if defined(CONFIG_OF_LIBFDT)
38 int fixed_sdram(void);
39 void sdram_init(void);
41 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
42 void ddr_enable_ecc(unsigned int dram_size
);
45 int board_early_init_f (void)
47 volatile u8
* bcsr
= (volatile u8
*)CFG_BCSR
;
49 /* Enable flash write */
52 #ifdef CFG_USE_MPC834XSYS_USB_PHY
53 /* Use USB PHY on SYS board */
60 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
62 long int initdram (int board_type
)
64 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
67 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
)im
)
70 /* DDR SDRAM - Main SODIMM */
71 im
->sysconf
.ddrlaw
[0].bar
= CFG_DDR_BASE
& LAWBAR_BAR
;
72 #if defined(CONFIG_SPD_EEPROM)
75 msize
= fixed_sdram();
78 * Initialize SDRAM if it is on local bus.
82 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
84 * Initialize and enable DDR ECC.
86 ddr_enable_ecc(msize
* 1024 * 1024);
89 /* return total bus SDRAM size(bytes) -- DDR */
90 return (msize
* 1024 * 1024);
93 #if !defined(CONFIG_SPD_EEPROM)
94 /*************************************************************************
95 * fixed sdram init -- doesn't use serial presence detect.
96 ************************************************************************/
99 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
104 msize
= CFG_DDR_SIZE
;
105 for (ddr_size
= msize
<< 20, ddr_size_log2
= 0;
107 ddr_size
= ddr_size
>>1, ddr_size_log2
++) {
112 im
->sysconf
.ddrlaw
[0].bar
= ((CFG_DDR_SDRAM_BASE
>>12) & 0xfffff);
113 im
->sysconf
.ddrlaw
[0].ar
= LAWAR_EN
| ((ddr_size_log2
- 1) & LAWAR_SIZE
);
115 #if (CFG_DDR_SIZE != 256)
116 #warning Currenly any ddr size other than 256 is not supported
119 im
->ddr
.csbnds
[2].csbnds
= CFG_DDR_CS2_BNDS
;
120 im
->ddr
.cs_config
[2] = CFG_DDR_CS2_CONFIG
;
121 im
->ddr
.timing_cfg_0
= CFG_DDR_TIMING_0
;
122 im
->ddr
.timing_cfg_1
= CFG_DDR_TIMING_1
;
123 im
->ddr
.timing_cfg_2
= CFG_DDR_TIMING_2
;
124 im
->ddr
.timing_cfg_3
= CFG_DDR_TIMING_3
;
125 im
->ddr
.sdram_cfg
= CFG_DDR_SDRAM_CFG
;
126 im
->ddr
.sdram_cfg2
= CFG_DDR_SDRAM_CFG2
;
127 im
->ddr
.sdram_mode
= CFG_DDR_MODE
;
128 im
->ddr
.sdram_mode2
= CFG_DDR_MODE2
;
129 im
->ddr
.sdram_interval
= CFG_DDR_INTERVAL
;
130 im
->ddr
.sdram_clk_cntl
= CFG_DDR_CLK_CNTL
;
132 im
->ddr
.csbnds
[2].csbnds
= 0x0000000f;
133 im
->ddr
.cs_config
[2] = CFG_DDR_CONFIG
;
135 /* currently we use only one CS, so disable the other banks */
136 im
->ddr
.cs_config
[0] = 0;
137 im
->ddr
.cs_config
[1] = 0;
138 im
->ddr
.cs_config
[3] = 0;
140 im
->ddr
.timing_cfg_1
= CFG_DDR_TIMING_1
;
141 im
->ddr
.timing_cfg_2
= CFG_DDR_TIMING_2
;
145 #if defined(CONFIG_DDR_2T_TIMING)
148 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT
;
149 #if defined (CONFIG_DDR_32BIT)
150 /* for 32-bit mode burst length is 8 */
151 im
->ddr
.sdram_cfg
|= (SDRAM_CFG_32_BE
| SDRAM_CFG_8_BE
);
153 im
->ddr
.sdram_mode
= CFG_DDR_MODE
;
155 im
->ddr
.sdram_interval
= CFG_DDR_INTERVAL
;
159 /* enable DDR controller */
160 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
163 #endif/*!CFG_SPD_EEPROM*/
166 int checkboard (void)
168 puts("Board: Freescale MPC8349EMDS\n");
173 * if MPC8349EMDS is soldered with SDRAM
175 #if defined(CFG_BR2_PRELIM) \
176 && defined(CFG_OR2_PRELIM) \
177 && defined(CFG_LBLAWBAR2_PRELIM) \
178 && defined(CFG_LBLAWAR2_PRELIM)
180 * Initialize SDRAM memory on the Local Bus.
183 void sdram_init(void)
185 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
186 volatile lbus83xx_t
*lbc
= &immap
->lbus
;
187 uint
*sdram_addr
= (uint
*)CFG_LBC_SDRAM_BASE
;
190 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
193 /* setup mtrpt, lsrt and lbcr for LB bus */
194 lbc
->lbcr
= CFG_LBC_LBCR
;
195 lbc
->mrtpr
= CFG_LBC_MRTPR
;
196 lbc
->lsrt
= CFG_LBC_LSRT
;
200 * Configure the SDRAM controller Machine Mode Register.
202 lbc
->lsdmr
= CFG_LBC_LSDMR_5
; /* 0x40636733; normal operation */
204 lbc
->lsdmr
= CFG_LBC_LSDMR_1
; /* 0x68636733; precharge all the banks */
209 lbc
->lsdmr
= CFG_LBC_LSDMR_2
; /* 0x48636733; auto refresh */
236 /* 0x58636733; mode register write operation */
237 lbc
->lsdmr
= CFG_LBC_LSDMR_4
;
242 lbc
->lsdmr
= CFG_LBC_LSDMR_5
; /* 0x40636733; normal operation */
248 void sdram_init(void)
254 * The following are used to control the SPI chip selects for the SPI command.
256 #ifdef CONFIG_HARD_SPI
258 #define SPI_CS_MASK 0x80000000
260 void spi_eeprom_chipsel(int cs
)
262 volatile gpio83xx_t
*iopd
= &((immap_t
*)CFG_IMMR
)->gpio
[0];
265 iopd
->dat
&= ~SPI_CS_MASK
;
267 iopd
->dat
|= SPI_CS_MASK
;
271 * The SPI command uses this table of functions for controlling the SPI
274 spi_chipsel_type spi_chipsel
[] = {
277 int spi_chipsel_cnt
= sizeof(spi_chipsel
) / sizeof(spi_chipsel
[0]);
279 #endif /* CONFIG_HARD_SPI */
281 #if defined(CONFIG_OF_BOARD_SETUP)
282 void ft_board_setup(void *blob
, bd_t
*bd
)
284 ft_cpu_setup(blob
, bd
);
286 ft_pci_setup(blob
, bd
);