2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/global_data.h>
30 #include <asm/mpc8349_pci.h>
32 #if defined(CONFIG_OF_LIBFDT)
34 #include <fdt_support.h>
37 DECLARE_GLOBAL_DATA_PTR
;
39 /* System RAM mapped to PCI space */
40 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
41 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
43 #ifndef CONFIG_PCI_PNP
44 static struct pci_config_table pci_mpc8349itx_config_table
[] = {
52 pci_cfgfunc_config_device
,
56 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
}
62 static struct pci_controller pci_hose
[] = {
64 #ifndef CONFIG_PCI_PNP
65 config_table
:pci_mpc8349itx_config_table
,
69 #ifndef CONFIG_PCI_PNP
70 config_table
:pci_mpc8349itx_config_table
,
75 /**************************************************************************
78 * NOTICE: PCI2 is not currently supported
81 void pci_init_board(void)
83 volatile immap_t
*immr
;
84 volatile clk83xx_t
*clk
;
85 volatile law83xx_t
*pci_law
;
86 volatile pot83xx_t
*pci_pot
;
87 volatile pcictrl83xx_t
*pci_ctrl
;
88 volatile pciconf83xx_t
*pci_conf
;
93 struct pci_controller
*hose
;
95 immr
= (immap_t
*) CONFIG_SYS_IMMR
;
96 clk
= (clk83xx_t
*) & immr
->clk
;
97 pci_law
= immr
->sysconf
.pcilaw
;
98 pci_pot
= immr
->ios
.pot
;
99 pci_ctrl
= immr
->pci_ctrl
;
100 pci_conf
= immr
->pci_conf
;
105 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
111 #ifdef CONFIG_HARD_I2C
113 /* Read the PCI_M66EN jumper setting */
114 if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2
, 0, 0, ®8
, sizeof(reg8
)) == 0) ||
115 (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2
, 0, 0, ®8
, sizeof(reg8
)) == 0)) {
116 if (reg8
& I2C_8574_PCI66
)
117 clk
->occr
= 0xff000000; /* 66 MHz PCI */
119 clk
->occr
= 0xff600001; /* 33 MHz PCI */
121 clk
->occr
= 0xff600001; /* 33 MHz PCI */
124 clk
->occr
= 0xff000000; /* 66 MHz PCI */
130 * Release PCI RST Output signal
136 #ifdef CONFIG_MPC83XX_PCI2
142 /* We need to wait at least a 1sec based on PCI specs */
146 for (i
= 0; i
< 1000; i
++)
151 * Configure PCI Local Access Windows
153 pci_law
[0].bar
= CONFIG_SYS_PCI1_MEM_PHYS
& LAWBAR_BAR
;
154 pci_law
[0].ar
= LAWAR_EN
| LAWAR_SIZE_1G
;
156 pci_law
[1].bar
= CONFIG_SYS_PCI1_IO_PHYS
& LAWBAR_BAR
;
157 pci_law
[1].ar
= LAWAR_EN
| LAWAR_SIZE_32M
;
160 * Configure PCI Outbound Translation Windows
163 /* PCI1 mem space - prefetch */
164 pci_pot
[0].potar
= (CONFIG_SYS_PCI1_MEM_BASE
>> 12) & POTAR_TA_MASK
;
165 pci_pot
[0].pobar
= (CONFIG_SYS_PCI1_MEM_PHYS
>> 12) & POBAR_BA_MASK
;
166 pci_pot
[0].pocmr
= POCMR_EN
| POCMR_PREFETCH_EN
| POCMR_CM_256M
;
169 pci_pot
[1].potar
= (CONFIG_SYS_PCI1_IO_BASE
>> 12) & POTAR_TA_MASK
;
170 pci_pot
[1].pobar
= (CONFIG_SYS_PCI1_IO_PHYS
>> 12) & POBAR_BA_MASK
;
171 pci_pot
[1].pocmr
= POCMR_EN
| POCMR_IO
| POCMR_CM_16M
;
173 /* PCI1 mmio - non-prefetch mem space */
174 pci_pot
[2].potar
= (CONFIG_SYS_PCI1_MMIO_BASE
>> 12) & POTAR_TA_MASK
;
175 pci_pot
[2].pobar
= (CONFIG_SYS_PCI1_MMIO_PHYS
>> 12) & POBAR_BA_MASK
;
176 pci_pot
[2].pocmr
= POCMR_EN
| POCMR_CM_256M
;
179 * Configure PCI Inbound Translation Windows
182 /* we need RAM mapped to PCI space for the devices to
183 * access main memory */
184 pci_ctrl
[0].pitar1
= 0x0;
185 pci_ctrl
[0].pibar1
= 0x0;
186 pci_ctrl
[0].piebar1
= 0x0;
187 pci_ctrl
[0].piwar1
= PIWAR_EN
| PIWAR_PF
| PIWAR_RTT_SNOOP
|
188 PIWAR_WTT_SNOOP
| (__ilog2(gd
->ram_size
) - 1);
190 hose
->first_busno
= 0;
191 hose
->last_busno
= 0xff;
193 /* PCI memory prefetch space */
194 pci_set_region(hose
->regions
+ 0,
195 CONFIG_SYS_PCI1_MEM_BASE
,
196 CONFIG_SYS_PCI1_MEM_PHYS
,
197 CONFIG_SYS_PCI1_MEM_SIZE
, PCI_REGION_MEM
| PCI_REGION_PREFETCH
);
199 /* PCI memory space */
200 pci_set_region(hose
->regions
+ 1,
201 CONFIG_SYS_PCI1_MMIO_BASE
,
202 CONFIG_SYS_PCI1_MMIO_PHYS
, CONFIG_SYS_PCI1_MMIO_SIZE
, PCI_REGION_MEM
);
205 pci_set_region(hose
->regions
+ 2,
206 CONFIG_SYS_PCI1_IO_BASE
,
207 CONFIG_SYS_PCI1_IO_PHYS
, CONFIG_SYS_PCI1_IO_SIZE
, PCI_REGION_IO
);
209 /* System memory space */
210 pci_set_region(hose
->regions
+ 3,
211 CONFIG_PCI_SYS_MEM_BUS
,
212 CONFIG_PCI_SYS_MEM_PHYS
,
213 gd
->ram_size
, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
215 hose
->region_count
= 4;
217 pci_setup_indirect(hose
,
218 (CONFIG_SYS_IMMR
+ 0x8300), (CONFIG_SYS_IMMR
+ 0x8304));
220 pci_register_hose(hose
);
223 * Write to Command register
226 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
227 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, ®16
);
228 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
229 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
232 * Clear non-reserved bits in status register.
234 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
235 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
236 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
238 #ifdef CONFIG_PCI_SCAN_SHOW
239 printf("PCI: Bus Dev VenId DevId Class Int\n");
244 hose
->last_busno
= pci_hose_scan(hose
);
246 #ifdef CONFIG_MPC83XX_PCI2
250 * Configure PCI Outbound Translation Windows
253 /* PCI2 mem space - prefetch */
254 pci_pot
[3].potar
= (CONFIG_SYS_PCI2_MEM_BASE
>> 12) & POTAR_TA_MASK
;
255 pci_pot
[3].pobar
= (CONFIG_SYS_PCI2_MEM_PHYS
>> 12) & POBAR_BA_MASK
;
256 pci_pot
[3].pocmr
= POCMR_EN
| POCMR_PCI2
| POCMR_PREFETCH_EN
| POCMR_CM_256M
;
259 pci_pot
[4].potar
= (CONFIG_SYS_PCI2_IO_BASE
>> 12) & POTAR_TA_MASK
;
260 pci_pot
[4].pobar
= (CONFIG_SYS_PCI2_IO_PHYS
>> 12) & POBAR_BA_MASK
;
261 pci_pot
[4].pocmr
= POCMR_EN
| POCMR_PCI2
| POCMR_IO
| POCMR_CM_16M
;
263 /* PCI2 mmio - non-prefetch mem space */
264 pci_pot
[5].potar
= (CONFIG_SYS_PCI2_MMIO_BASE
>> 12) & POTAR_TA_MASK
;
265 pci_pot
[5].pobar
= (CONFIG_SYS_PCI2_MMIO_PHYS
>> 12) & POBAR_BA_MASK
;
266 pci_pot
[5].pocmr
= POCMR_EN
| POCMR_PCI2
| POCMR_CM_256M
;
269 * Configure PCI Inbound Translation Windows
272 /* we need RAM mapped to PCI space for the devices to
273 * access main memory */
274 pci_ctrl
[1].pitar1
= 0x0;
275 pci_ctrl
[1].pibar1
= 0x0;
276 pci_ctrl
[1].piebar1
= 0x0;
278 PIWAR_EN
| PIWAR_PF
| PIWAR_RTT_SNOOP
| PIWAR_WTT_SNOOP
|
279 (__ilog2(gd
->ram_size
) - 1);
281 hose
->first_busno
= pci_hose
[0].last_busno
+ 1;
282 hose
->last_busno
= 0xff;
284 /* PCI memory prefetch space */
285 pci_set_region(hose
->regions
+ 0,
286 CONFIG_SYS_PCI2_MEM_BASE
,
287 CONFIG_SYS_PCI2_MEM_PHYS
,
288 CONFIG_SYS_PCI2_MEM_SIZE
, PCI_REGION_MEM
| PCI_REGION_PREFETCH
);
290 /* PCI memory space */
291 pci_set_region(hose
->regions
+ 1,
292 CONFIG_SYS_PCI2_MMIO_BASE
,
293 CONFIG_SYS_PCI2_MMIO_PHYS
, CONFIG_SYS_PCI2_MMIO_SIZE
, PCI_REGION_MEM
);
296 pci_set_region(hose
->regions
+ 2,
297 CONFIG_SYS_PCI2_IO_BASE
,
298 CONFIG_SYS_PCI2_IO_PHYS
, CONFIG_SYS_PCI2_IO_SIZE
, PCI_REGION_IO
);
300 /* System memory space */
301 pci_set_region(hose
->regions
+ 3,
302 CONFIG_PCI_SYS_MEM_BUS
,
303 CONFIG_PCI_SYS_MEM_PHYS
,
304 gd
->ram_size
, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
306 hose
->region_count
= 4;
308 pci_setup_indirect(hose
,
309 (CONFIG_SYS_IMMR
+ 0x8380), (CONFIG_SYS_IMMR
+ 0x8384));
311 pci_register_hose(hose
);
314 * Write to Command register
317 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
318 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, ®16
);
319 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
320 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
323 * Clear non-reserved bits in status register.
325 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
326 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
327 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
332 hose
->last_busno
= pci_hose_scan(hose
);
336 #if defined(CONFIG_OF_LIBFDT)
337 void ft_pci_setup(void *blob
, bd_t
*bd
)
343 nodeoffset
= fdt_path_offset(blob
, "/aliases");
344 if (nodeoffset
>= 0) {
345 path
= fdt_getprop(blob
, nodeoffset
, "pci0", NULL
);
347 tmp
[0] = cpu_to_be32(pci_hose
[0].first_busno
);
348 tmp
[1] = cpu_to_be32(pci_hose
[0].last_busno
);
349 do_fixup_by_path(blob
, path
, "bus-range",
350 &tmp
, sizeof(tmp
), 1);
352 tmp
[0] = cpu_to_be32(gd
->pci_clk
);
353 do_fixup_by_path(blob
, path
, "clock-frequency",
354 &tmp
, sizeof(tmp
[0]), 1);
356 #ifdef CONFIG_MPC83XX_PCI2
357 path
= fdt_getprop(blob
, nodeoffset
, "pci1", NULL
);
359 tmp
[0] = cpu_to_be32(pci_hose
[0].first_busno
);
360 tmp
[1] = cpu_to_be32(pci_hose
[0].last_busno
);
361 do_fixup_by_path(blob
, path
, "bus-range",
362 &tmp
, sizeof(tmp
), 1);
364 tmp
[0] = cpu_to_be32(gd
->pci_clk
);
365 do_fixup_by_path(blob
, path
, "clock-frequency",
366 &tmp
, sizeof(tmp
[0]), 1);
371 #endif /* CONFIG_OF_LIBFDT */
372 #endif /* CONFIG_PCI */