2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
19 #if defined(CONFIG_PCI)
22 #include <spd_sdram.h>
24 #if defined(CONFIG_OF_LIBFDT)
27 #if defined(CONFIG_PQ_MDS_PIB)
28 #include "../common/pq-mds-pib.h"
31 const qe_iop_conf_t qe_iop_conf_tab
[] = {
33 {0, 3, 1, 0, 1}, /* TxD0 */
34 {0, 4, 1, 0, 1}, /* TxD1 */
35 {0, 5, 1, 0, 1}, /* TxD2 */
36 {0, 6, 1, 0, 1}, /* TxD3 */
37 {1, 6, 1, 0, 3}, /* TxD4 */
38 {1, 7, 1, 0, 1}, /* TxD5 */
39 {1, 9, 1, 0, 2}, /* TxD6 */
40 {1, 10, 1, 0, 2}, /* TxD7 */
41 {0, 9, 2, 0, 1}, /* RxD0 */
42 {0, 10, 2, 0, 1}, /* RxD1 */
43 {0, 11, 2, 0, 1}, /* RxD2 */
44 {0, 12, 2, 0, 1}, /* RxD3 */
45 {0, 13, 2, 0, 1}, /* RxD4 */
46 {1, 1, 2, 0, 2}, /* RxD5 */
47 {1, 0, 2, 0, 2}, /* RxD6 */
48 {1, 4, 2, 0, 2}, /* RxD7 */
49 {0, 7, 1, 0, 1}, /* TX_EN */
50 {0, 8, 1, 0, 1}, /* TX_ER */
51 {0, 15, 2, 0, 1}, /* RX_DV */
52 {0, 16, 2, 0, 1}, /* RX_ER */
53 {0, 0, 2, 0, 1}, /* RX_CLK */
54 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
55 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
57 {0, 17, 1, 0, 1}, /* TxD0 */
58 {0, 18, 1, 0, 1}, /* TxD1 */
59 {0, 19, 1, 0, 1}, /* TxD2 */
60 {0, 20, 1, 0, 1}, /* TxD3 */
61 {1, 2, 1, 0, 1}, /* TxD4 */
62 {1, 3, 1, 0, 2}, /* TxD5 */
63 {1, 5, 1, 0, 3}, /* TxD6 */
64 {1, 8, 1, 0, 3}, /* TxD7 */
65 {0, 23, 2, 0, 1}, /* RxD0 */
66 {0, 24, 2, 0, 1}, /* RxD1 */
67 {0, 25, 2, 0, 1}, /* RxD2 */
68 {0, 26, 2, 0, 1}, /* RxD3 */
69 {0, 27, 2, 0, 1}, /* RxD4 */
70 {1, 12, 2, 0, 2}, /* RxD5 */
71 {1, 13, 2, 0, 3}, /* RxD6 */
72 {1, 11, 2, 0, 2}, /* RxD7 */
73 {0, 21, 1, 0, 1}, /* TX_EN */
74 {0, 22, 1, 0, 1}, /* TX_ER */
75 {0, 29, 2, 0, 1}, /* RX_DV */
76 {0, 30, 2, 0, 1}, /* RX_ER */
77 {0, 31, 2, 0, 1}, /* RX_CLK */
78 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
79 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
81 {0, 1, 3, 0, 2}, /* MDIO */
82 {0, 2, 1, 0, 1}, /* MDC */
84 {5, 0, 1, 0, 2}, /* UART2_SOUT */
85 {5, 1, 2, 0, 3}, /* UART2_CTS */
86 {5, 2, 1, 0, 1}, /* UART2_RTS */
87 {5, 3, 2, 0, 2}, /* UART2_SIN */
89 {0, 0, 0, 0, QE_IOP_TAB_END
}, /* END of table */
92 int board_early_init_f(void)
95 u8
*bcsr
= (u8
*)CONFIG_SYS_BCSR
;
96 const immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
98 /* Enable flash write */
101 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
102 if (REVID_MAJOR(immr
->sysconf
.spridr
) == 2)
105 /* Enable second UART */
111 int board_early_init_r(void)
113 #ifdef CONFIG_PQ_MDS_PIB
119 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
120 extern void ddr_enable_ecc(unsigned int dram_size
);
122 int fixed_sdram(void);
123 void sdram_init(void);
125 phys_size_t
initdram(int board_type
)
127 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
130 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
133 /* DDR SDRAM - Main SODIMM */
134 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_BASE
& LAWBAR_BAR
;
135 #if defined(CONFIG_SPD_EEPROM)
138 msize
= fixed_sdram();
141 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
143 * Initialize DDR ECC byte
145 ddr_enable_ecc(msize
* 1024 * 1024);
148 * Initialize SDRAM if it is on local bus.
152 /* return total bus SDRAM size(bytes) -- DDR */
153 return (msize
* 1024 * 1024);
156 #if !defined(CONFIG_SPD_EEPROM)
157 /*************************************************************************
158 * fixed sdram init -- doesn't use serial presence detect.
159 ************************************************************************/
160 int fixed_sdram(void)
162 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
167 msize
= CONFIG_SYS_DDR_SIZE
;
168 for (ddr_size
= msize
<< 20, ddr_size_log2
= 0;
169 (ddr_size
> 1); ddr_size
= ddr_size
>> 1, ddr_size_log2
++) {
174 im
->sysconf
.ddrlaw
[0].ar
=
175 LAWAR_EN
| ((ddr_size_log2
- 1) & LAWAR_SIZE
);
176 #if (CONFIG_SYS_DDR_SIZE != 256)
177 #warning Currenly any ddr size other than 256 is not supported
180 im
->ddr
.csbnds
[0].csbnds
= CONFIG_SYS_DDR_CS0_BNDS
;
181 im
->ddr
.cs_config
[0] = CONFIG_SYS_DDR_CS0_CONFIG
;
182 im
->ddr
.timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
183 im
->ddr
.timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
184 im
->ddr
.timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
185 im
->ddr
.timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
186 im
->ddr
.sdram_cfg
= CONFIG_SYS_DDR_SDRAM_CFG
;
187 im
->ddr
.sdram_cfg2
= CONFIG_SYS_DDR_SDRAM_CFG2
;
188 im
->ddr
.sdram_mode
= CONFIG_SYS_DDR_MODE
;
189 im
->ddr
.sdram_mode2
= CONFIG_SYS_DDR_MODE2
;
190 im
->ddr
.sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
191 im
->ddr
.sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CNTL
;
193 im
->ddr
.csbnds
[0].csbnds
= 0x00000007;
194 im
->ddr
.csbnds
[1].csbnds
= 0x0008000f;
196 im
->ddr
.cs_config
[0] = CONFIG_SYS_DDR_CONFIG
;
197 im
->ddr
.cs_config
[1] = CONFIG_SYS_DDR_CONFIG
;
199 im
->ddr
.timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
200 im
->ddr
.timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
201 im
->ddr
.sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
203 im
->ddr
.sdram_mode
= CONFIG_SYS_DDR_MODE
;
204 im
->ddr
.sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
207 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
211 #endif /*!CONFIG_SYS_SPD_EEPROM */
215 puts("Board: Freescale MPC8360EMDS\n");
220 * if MPC8360EMDS is soldered with SDRAM
222 #if defined(CONFIG_SYS_BR2_PRELIM) \
223 && defined(CONFIG_SYS_OR2_PRELIM) \
224 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
225 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
227 * Initialize SDRAM memory on the Local Bus.
230 void sdram_init(void)
232 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
233 volatile lbus83xx_t
*lbc
= &immap
->lbus
;
234 uint
*sdram_addr
= (uint
*) CONFIG_SYS_LBC_SDRAM_BASE
;
237 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
239 /*setup mtrpt, lsrt and lbcr for LB bus */
240 lbc
->lbcr
= CONFIG_SYS_LBC_LBCR
;
241 lbc
->mrtpr
= CONFIG_SYS_LBC_MRTPR
;
242 lbc
->lsrt
= CONFIG_SYS_LBC_LSRT
;
246 * Configure the SDRAM controller Machine Mode Register.
248 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_5
; /* Normal Operation */
249 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_1
; /* Precharge All Banks */
255 * We need do 8 times auto refresh operation.
257 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_2
;
259 *sdram_addr
= 0xff; /* 1 times */
261 *sdram_addr
= 0xff; /* 2 times */
263 *sdram_addr
= 0xff; /* 3 times */
265 *sdram_addr
= 0xff; /* 4 times */
267 *sdram_addr
= 0xff; /* 5 times */
269 *sdram_addr
= 0xff; /* 6 times */
271 *sdram_addr
= 0xff; /* 7 times */
273 *sdram_addr
= 0xff; /* 8 times */
276 /* Mode register write operation */
277 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_4
;
279 *(sdram_addr
+ 0xcc) = 0xff;
282 /* Normal operation */
283 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_5
| 0x40000000;
289 void sdram_init(void)
294 #if defined(CONFIG_OF_BOARD_SETUP)
295 void ft_board_setup(void *blob
, bd_t
*bd
)
297 const immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
299 ft_cpu_setup(blob
, bd
);
301 ft_pci_setup(blob
, bd
);
304 * mpc8360ea pb mds errata 2: RGMII timing
305 * if on mpc8360ea rev. 2.1,
306 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
308 if ((REVID_MAJOR(immr
->sysconf
.spridr
) == 2) &&
309 (REVID_MINOR(immr
->sysconf
.spridr
) == 1)) {
314 nodeoffset
= fdt_path_offset(blob
, "/aliases");
315 if (nodeoffset
>= 0) {
316 #if defined(CONFIG_HAS_ETH0)
317 /* fixup UCC 1 if using rgmii-id mode */
318 prop
= fdt_getprop(blob
, nodeoffset
, "ethernet0", NULL
);
320 path
= fdt_path_offset(blob
, prop
);
321 prop
= fdt_getprop(blob
, path
,
322 "phy-connection-type", 0);
323 if (prop
&& (strcmp(prop
, "rgmii-id") == 0))
324 fdt_setprop(blob
, path
,
325 "phy-connection-type",
327 sizeof("rgmii-rxid"));
330 #if defined(CONFIG_HAS_ETH1)
331 /* fixup UCC 2 if using rgmii-id mode */
332 prop
= fdt_getprop(blob
, nodeoffset
, "ethernet1", NULL
);
334 path
= fdt_path_offset(blob
, prop
);
335 prop
= fdt_getprop(blob
, path
,
336 "phy-connection-type", 0);
337 if (prop
&& (strcmp(prop
, "rgmii-id") == 0))
338 fdt_setprop(blob
, path
,
339 "phy-connection-type",
341 sizeof("rgmii-rxid"));