board/freescale/mpc8360emds/mpc8360emds.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  * Dave Liu <daveliu@freescale.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <common.h>
  15 #include <ioports.h>
  16 #include <mpc83xx.h>
  17 #include <i2c.h>
  18 #include <miiphy.h>
  19 #if defined(CONFIG_PCI)
  20 #include <pci.h>
  21 #endif
  22 #include <spd_sdram.h>
  23 #include <asm/mmu.h>
  24 #if defined(CONFIG_OF_LIBFDT)
  25 #include <libfdt.h>
  26 #endif
  27 #if defined(CONFIG_PQ_MDS_PIB)
  28 #include "../common/pq-mds-pib.h"
  29 #endif
  30
  31 const qe_iop_conf_t qe_iop_conf_tab[] = {
  32         /* GETH1 */
  33         {0,  3, 1, 0, 1}, /* TxD0 */
  34         {0,  4, 1, 0, 1}, /* TxD1 */
  35         {0,  5, 1, 0, 1}, /* TxD2 */
  36         {0,  6, 1, 0, 1}, /* TxD3 */
  37         {1,  6, 1, 0, 3}, /* TxD4 */
  38         {1,  7, 1, 0, 1}, /* TxD5 */
  39         {1,  9, 1, 0, 2}, /* TxD6 */
  40         {1, 10, 1, 0, 2}, /* TxD7 */
  41         {0,  9, 2, 0, 1}, /* RxD0 */
  42         {0, 10, 2, 0, 1}, /* RxD1 */
  43         {0, 11, 2, 0, 1}, /* RxD2 */
  44         {0, 12, 2, 0, 1}, /* RxD3 */
  45         {0, 13, 2, 0, 1}, /* RxD4 */
  46         {1,  1, 2, 0, 2}, /* RxD5 */
  47         {1,  0, 2, 0, 2}, /* RxD6 */
  48         {1,  4, 2, 0, 2}, /* RxD7 */
  49         {0,  7, 1, 0, 1}, /* TX_EN */
  50         {0,  8, 1, 0, 1}, /* TX_ER */
  51         {0, 15, 2, 0, 1}, /* RX_DV */
  52         {0, 16, 2, 0, 1}, /* RX_ER */
  53         {0,  0, 2, 0, 1}, /* RX_CLK */
  54         {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  55         {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  56         /* GETH2 */
  57         {0, 17, 1, 0, 1}, /* TxD0 */
  58         {0, 18, 1, 0, 1}, /* TxD1 */
  59         {0, 19, 1, 0, 1}, /* TxD2 */
  60         {0, 20, 1, 0, 1}, /* TxD3 */
  61         {1,  2, 1, 0, 1}, /* TxD4 */
  62         {1,  3, 1, 0, 2}, /* TxD5 */
  63         {1,  5, 1, 0, 3}, /* TxD6 */
  64         {1,  8, 1, 0, 3}, /* TxD7 */
  65         {0, 23, 2, 0, 1}, /* RxD0 */
  66         {0, 24, 2, 0, 1}, /* RxD1 */
  67         {0, 25, 2, 0, 1}, /* RxD2 */
  68         {0, 26, 2, 0, 1}, /* RxD3 */
  69         {0, 27, 2, 0, 1}, /* RxD4 */
  70         {1, 12, 2, 0, 2}, /* RxD5 */
  71         {1, 13, 2, 0, 3}, /* RxD6 */
  72         {1, 11, 2, 0, 2}, /* RxD7 */
  73         {0, 21, 1, 0, 1}, /* TX_EN */
  74         {0, 22, 1, 0, 1}, /* TX_ER */
  75         {0, 29, 2, 0, 1}, /* RX_DV */
  76         {0, 30, 2, 0, 1}, /* RX_ER */
  77         {0, 31, 2, 0, 1}, /* RX_CLK */
  78         {2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
  79         {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  80
  81         {0,  1, 3, 0, 2}, /* MDIO */
  82         {0,  2, 1, 0, 1}, /* MDC */
  83
  84         {5,  0, 1, 0, 2}, /* UART2_SOUT */
  85         {5,  1, 2, 0, 3}, /* UART2_CTS */
  86         {5,  2, 1, 0, 1}, /* UART2_RTS */
  87         {5,  3, 2, 0, 2}, /* UART2_SIN */
  88
  89         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  90 };
  91
  92 int board_early_init_f(void)
  93 {
  94
  95         u8 *bcsr = (u8 *)CFG_BCSR;
  96         const immap_t *immr = (immap_t *)CFG_IMMR;
  97
  98         /* Enable flash write */
  99         bcsr[0xa] &= ~0x04;
 100
 101         /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
 102         if (immr->sysconf.spridr == SPR_8360_REV20 ||
 103             immr->sysconf.spridr == SPR_8360E_REV20 ||
 104             immr->sysconf.spridr == SPR_8360_REV21 ||
 105             immr->sysconf.spridr == SPR_8360E_REV21)
 106                 bcsr[0xe] = 0x30;
 107
 108         /* Enable second UART */
 109         bcsr[0x9] &= ~0x01;
 110
 111         return 0;
 112 }
 113
 114 int board_early_init_r(void)
 115 {
 116 #ifdef CONFIG_PQ_MDS_PIB
 117         pib_init();
 118 #endif
 119         return 0;
 120 }
 121
 122 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 123 extern void ddr_enable_ecc(unsigned int dram_size);
 124 #endif
 125 int fixed_sdram(void);
 126 void sdram_init(void);
 127
 128 long int initdram(int board_type)
 129 {
 130         volatile immap_t *im = (immap_t *) CFG_IMMR;
 131         u32 msize = 0;
 132
 133         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 134                 return -1;
 135
 136         /* DDR SDRAM - Main SODIMM */
 137         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 138 #if defined(CONFIG_SPD_EEPROM)
 139         msize = spd_sdram();
 140 #else
 141         msize = fixed_sdram();
 142 #endif
 143
 144 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 145         /*
 146          * Initialize DDR ECC byte
 147          */
 148         ddr_enable_ecc(msize * 1024 * 1024);
 149 #endif
 150         /*
 151          * Initialize SDRAM if it is on local bus.
 152          */
 153         sdram_init();
 154
 155         /* return total bus SDRAM size(bytes)  -- DDR */
 156         return (msize * 1024 * 1024);
 157 }
 158
 159 #if !defined(CONFIG_SPD_EEPROM)
 160 /*************************************************************************
 161  *  fixed sdram init -- doesn't use serial presence detect.
 162  ************************************************************************/
 163 int fixed_sdram(void)
 164 {
 165         volatile immap_t *im = (immap_t *) CFG_IMMR;
 166         u32 msize = 0;
 167         u32 ddr_size;
 168         u32 ddr_size_log2;
 169
 170         msize = CFG_DDR_SIZE;
 171         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 172              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 173                 if (ddr_size & 1) {
 174                         return -1;
 175                 }
 176         }
 177         im->sysconf.ddrlaw[0].ar =
 178             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 179 #if (CFG_DDR_SIZE != 256)
 180 #warning Currenly any ddr size other than 256 is not supported
 181 #endif
 182 #ifdef CONFIG_DDR_II
 183         im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
 184         im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
 185         im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
 186         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 187         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 188         im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
 189         im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
 190         im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
 191         im->ddr.sdram_mode = CFG_DDR_MODE;
 192         im->ddr.sdram_mode2 = CFG_DDR_MODE2;
 193         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 194         im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
 195 #else
 196         im->ddr.csbnds[0].csbnds = 0x00000007;
 197         im->ddr.csbnds[1].csbnds = 0x0008000f;
 198
 199         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 200         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 201
 202         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 203         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 204         im->ddr.sdram_cfg = CFG_DDR_CONTROL;
 205
 206         im->ddr.sdram_mode = CFG_DDR_MODE;
 207         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 208 #endif
 209         udelay(200);
 210         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 211
 212         return msize;
 213 }
 214 #endif                          /*!CFG_SPD_EEPROM */
 215
 216 int checkboard(void)
 217 {
 218         puts("Board: Freescale MPC8360EMDS\n");
 219         return 0;
 220 }
 221
 222 /*
 223  * if MPC8360EMDS is soldered with SDRAM
 224  */
 225 #if defined(CFG_BR2_PRELIM)  \
 226         && defined(CFG_OR2_PRELIM) \
 227         && defined(CFG_LBLAWBAR2_PRELIM) \
 228         && defined(CFG_LBLAWAR2_PRELIM)
 229 /*
 230  * Initialize SDRAM memory on the Local Bus.
 231  */
 232
 233 void sdram_init(void)
 234 {
 235         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 236         volatile lbus83xx_t *lbc = &immap->lbus;
 237         uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 238
 239         /*
 240          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 241          */
 242         /*setup mtrpt, lsrt and lbcr for LB bus */
 243         lbc->lbcr = CFG_LBC_LBCR;
 244         lbc->mrtpr = CFG_LBC_MRTPR;
 245         lbc->lsrt = CFG_LBC_LSRT;
 246         asm("sync");
 247
 248         /*
 249          * Configure the SDRAM controller Machine Mode Register.
 250          */
 251         lbc->lsdmr = CFG_LBC_LSDMR_5;   /* Normal Operation */
 252         lbc->lsdmr = CFG_LBC_LSDMR_1;   /* Precharge All Banks */
 253         asm("sync");
 254         *sdram_addr = 0xff;
 255         udelay(100);
 256
 257         /*
 258          * We need do 8 times auto refresh operation.
 259          */
 260         lbc->lsdmr = CFG_LBC_LSDMR_2;
 261         asm("sync");
 262         *sdram_addr = 0xff;     /* 1 times */
 263         udelay(100);
 264         *sdram_addr = 0xff;     /* 2 times */
 265         udelay(100);
 266         *sdram_addr = 0xff;     /* 3 times */
 267         udelay(100);
 268         *sdram_addr = 0xff;     /* 4 times */
 269         udelay(100);
 270         *sdram_addr = 0xff;     /* 5 times */
 271         udelay(100);
 272         *sdram_addr = 0xff;     /* 6 times */
 273         udelay(100);
 274         *sdram_addr = 0xff;     /* 7 times */
 275         udelay(100);
 276         *sdram_addr = 0xff;     /* 8 times */
 277         udelay(100);
 278
 279         /* Mode register write operation */
 280         lbc->lsdmr = CFG_LBC_LSDMR_4;
 281         asm("sync");
 282         *(sdram_addr + 0xcc) = 0xff;
 283         udelay(100);
 284
 285         /* Normal operation */
 286         lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
 287         asm("sync");
 288         *sdram_addr = 0xff;
 289         udelay(100);
 290 }
 291 #else
 292 void sdram_init(void)
 293 {
 294 }
 295 #endif
 296
 297 #if defined(CONFIG_OF_BOARD_SETUP)
 298 void ft_board_setup(void *blob, bd_t *bd)
 299 {
 300         const immap_t *immr = (immap_t *)CFG_IMMR;
 301
 302         ft_cpu_setup(blob, bd);
 303 #ifdef CONFIG_PCI
 304         ft_pci_setup(blob, bd);
 305 #endif
 306         /*
 307          * mpc8360ea pb mds errata 2: RGMII timing
 308          * if on mpc8360ea rev. 2.1,
 309          * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
 310          */
 311         if (immr->sysconf.spridr == SPR_8360_REV21 ||
 312             immr->sysconf.spridr == SPR_8360E_REV21) {
 313                 int nodeoffset;
 314                 const char *prop;
 315                 int path;
 316
 317                 nodeoffset = fdt_path_offset(blob, "/aliases");
 318                 if (nodeoffset >= 0) {
 319 #if defined(CONFIG_HAS_ETH0)
 320                         /* fixup UCC 1 if using rgmii-id mode */
 321                         prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
 322                         if (prop) {
 323                                 path = fdt_path_offset(blob, prop);
 324                                 prop = fdt_getprop(blob, path,
 325                                                    "phy-connection-type", 0);
 326                                 if (prop && (strcmp(prop, "rgmii-id") == 0))
 327                                         fdt_setprop(blob, path,
 328                                                     "phy-connection-type",
 329                                                     "rgmii-rxid",
 330                                                     sizeof("rgmii-rxid"));
 331                         }
 332 #endif
 333 #if defined(CONFIG_HAS_ETH1)
 334                         /* fixup UCC 2 if using rgmii-id mode */
 335                         prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
 336                         if (prop) {
 337                                 path = fdt_path_offset(blob, prop);
 338                                 prop = fdt_getprop(blob, path,
 339                                                    "phy-connection-type", 0);
 340                                 if (prop && (strcmp(prop, "rgmii-id") == 0))
 341                                         fdt_setprop(blob, path,
 342                                                     "phy-connection-type",
 343                                                     "rgmii-rxid",
 344                                                     sizeof("rgmii-rxid"));
 345                         }
 346 #endif
 347                 }
 348         }
 349 }
 350 #endif