2 * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/fsl_mpc83xx_serdes.h>
13 #include <asm/fsl_enet.h>
14 #include <spd_sdram.h>
17 #include <fdt_support.h>
18 #include <fsl_esdhc.h>
22 #include "../common/pq-mds-pib.h"
24 int board_early_init_f(void)
26 u8
*bcsr
= (u8
*)CONFIG_SYS_BCSR
;
28 /* Enable flash write */
30 /* Clear all of the interrupt of BCSR */
33 #ifdef CONFIG_FSL_SERDES
34 immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
35 u32 spridr
= in_be32(&immr
->sysconf
.spridr
);
37 /* we check only part num, and don't look for CPU revisions */
38 switch (PARTID_NO_E(spridr
)) {
40 fsl_setup_serdes(CONFIG_FSL_SERDES1
, FSL_SERDES_PROTO_SATA
,
41 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
44 fsl_setup_serdes(CONFIG_FSL_SERDES1
, FSL_SERDES_PROTO_SGMII
,
45 FSL_SERDES_CLK_125
, FSL_SERDES_VDD_1V
);
48 fsl_setup_serdes(CONFIG_FSL_SERDES1
, FSL_SERDES_PROTO_SATA
,
49 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
50 fsl_setup_serdes(CONFIG_FSL_SERDES2
, FSL_SERDES_PROTO_SATA
,
51 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
54 printf("serdes not configured: unknown CPU part number: "
55 "%04x\n", spridr
>> 16);
58 #endif /* CONFIG_FSL_SERDES */
62 #ifdef CONFIG_FSL_ESDHC
63 int board_mmc_init(bd_t
*bd
)
65 struct immap __iomem
*im
= (struct immap __iomem
*)CONFIG_SYS_IMMR
;
66 u8
*bcsr
= (u8
*)CONFIG_SYS_BCSR
;
68 if (!hwconfig("esdhc"))
71 /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
74 /* Set proper bits in SICR to allow SD signals through */
75 clrsetbits_be32(&im
->sysconf
.sicrl
, SICRL_USB_B
, SICRL_USB_B_SD
);
76 clrsetbits_be32(&im
->sysconf
.sicrh
, SICRH_GPIO2_E
| SICRH_SPI
,
77 SICRH_GPIO2_E_SD
| SICRH_SPI_SD
);
79 return fsl_esdhc_mmc_init(bd
);
83 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
84 int board_eth_init(bd_t
*bd
)
86 struct fsl_pq_mdio_info mdio_info
;
87 struct tsec_info_struct tsec_info
[2];
88 struct immap __iomem
*im
= (struct immap __iomem
*)CONFIG_SYS_IMMR
;
89 u32 rcwh
= in_be32(&im
->reset
.rcwh
);
93 /* New line after Net: */
97 SET_STD_TSEC_INFO(tsec_info
[num
], 1);
99 printf(CONFIG_TSEC1_NAME
": ");
101 tsec_mode
= rcwh
& HRCWH_TSEC1M_MASK
;
102 if (tsec_mode
== HRCWH_TSEC1M_IN_RGMII
) {
104 /* this is default, no need to fixup */
105 } else if (tsec_mode
== HRCWH_TSEC1M_IN_SGMII
) {
107 tsec_info
[num
].phyaddr
= TSEC1_PHY_ADDR_SGMII
;
108 tsec_info
[num
].flags
= TSEC_GIGABIT
;
110 printf("unsupported PHY type\n");
115 SET_STD_TSEC_INFO(tsec_info
[num
], 2);
117 printf(CONFIG_TSEC2_NAME
": ");
119 tsec_mode
= rcwh
& HRCWH_TSEC2M_MASK
;
120 if (tsec_mode
== HRCWH_TSEC2M_IN_RGMII
) {
122 /* this is default, no need to fixup */
123 } else if (tsec_mode
== HRCWH_TSEC2M_IN_SGMII
) {
125 tsec_info
[num
].phyaddr
= TSEC2_PHY_ADDR_SGMII
;
126 tsec_info
[num
].flags
= TSEC_GIGABIT
;
128 printf("unsupported PHY type\n");
133 mdio_info
.regs
= (struct tsec_mii_mng
*)CONFIG_SYS_MDIO_BASE_ADDR
;
134 mdio_info
.name
= DEFAULT_MII_NAME
;
135 fsl_pq_mdio_init(bd
, &mdio_info
);
137 return tsec_eth_init(bd
, tsec_info
, num
);
140 static void __ft_tsec_fixup(void *blob
, bd_t
*bd
, const char *alias
,
147 off
= fdt_path_offset(blob
, alias
);
149 printf("WARNING: could not find %s alias: %s.\n", alias
,
154 err
= fdt_fixup_phy_connection(blob
, off
, PHY_INTERFACE_MODE_SGMII
);
157 printf("WARNING: could not set phy-connection-type for %s: "
158 "%s.\n", alias
, fdt_strerror(err
));
162 ph
= (u32
*)fdt_getprop(blob
, off
, "phy-handle", 0);
164 printf("WARNING: could not get phy-handle for %s.\n",
169 off
= fdt_node_offset_by_phandle(blob
, *ph
);
171 printf("WARNING: could not get phy node for %s: %s\n", alias
,
176 phy_addr
= cpu_to_fdt32(phy_addr
);
177 err
= fdt_setprop(blob
, off
, "reg", &phy_addr
, sizeof(phy_addr
));
179 printf("WARNING: could not set phy node's reg for %s: "
180 "%s.\n", alias
, fdt_strerror(err
));
185 static void ft_tsec_fixup(void *blob
, bd_t
*bd
)
187 struct immap __iomem
*im
= (struct immap __iomem
*)CONFIG_SYS_IMMR
;
188 u32 rcwh
= in_be32(&im
->reset
.rcwh
);
192 tsec_mode
= rcwh
& HRCWH_TSEC1M_MASK
;
193 if (tsec_mode
== HRCWH_TSEC1M_IN_SGMII
)
194 __ft_tsec_fixup(blob
, bd
, "ethernet0", TSEC1_PHY_ADDR_SGMII
);
198 tsec_mode
= rcwh
& HRCWH_TSEC2M_MASK
;
199 if (tsec_mode
== HRCWH_TSEC2M_IN_SGMII
)
200 __ft_tsec_fixup(blob
, bd
, "ethernet1", TSEC2_PHY_ADDR_SGMII
);
204 static inline void ft_tsec_fixup(void *blob
, bd_t
*bd
) {}
205 #endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
207 int board_early_init_r(void)
209 #ifdef CONFIG_PQ_MDS_PIB
215 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
216 extern void ddr_enable_ecc(unsigned int dram_size
);
218 int fixed_sdram(void);
220 phys_size_t
initdram(int board_type
)
222 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
225 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
228 #if defined(CONFIG_SPD_EEPROM)
231 msize
= fixed_sdram();
234 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
235 /* Initialize DDR ECC byte */
236 ddr_enable_ecc(msize
* 1024 * 1024);
239 /* return total bus DDR size(bytes) */
240 return (msize
* 1024 * 1024);
243 #if !defined(CONFIG_SPD_EEPROM)
244 /*************************************************************************
245 * fixed sdram init -- doesn't use serial presence detect.
246 ************************************************************************/
247 int fixed_sdram(void)
249 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
250 u32 msize
= CONFIG_SYS_DDR_SIZE
* 1024 * 1024;
251 u32 msize_log2
= __ilog2(msize
);
253 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_SDRAM_BASE
& 0xfffff000;
254 im
->sysconf
.ddrlaw
[0].ar
= LBLAWAR_EN
| (msize_log2
- 1);
256 #if (CONFIG_SYS_DDR_SIZE != 512)
257 #warning Currenly any ddr size other than 512 is not supported
259 im
->sysconf
.ddrcdr
= CONFIG_SYS_DDRCDR_VALUE
;
262 im
->ddr
.sdram_clk_cntl
= CONFIG_SYS_DDR_SDRAM_CLK_CNTL
;
265 im
->ddr
.csbnds
[0].csbnds
= CONFIG_SYS_DDR_CS0_BNDS
;
266 im
->ddr
.cs_config
[0] = CONFIG_SYS_DDR_CS0_CONFIG
;
269 im
->ddr
.timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
270 im
->ddr
.timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
271 im
->ddr
.timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
272 im
->ddr
.timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
273 im
->ddr
.sdram_cfg
= CONFIG_SYS_DDR_SDRAM_CFG
;
274 im
->ddr
.sdram_cfg2
= CONFIG_SYS_DDR_SDRAM_CFG2
;
275 im
->ddr
.sdram_mode
= CONFIG_SYS_DDR_MODE
;
276 im
->ddr
.sdram_mode2
= CONFIG_SYS_DDR_MODE2
;
277 im
->ddr
.sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
278 __asm__
__volatile__("sync");
281 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
283 return CONFIG_SYS_DDR_SIZE
;
285 #endif /*!CONFIG_SYS_SPD_EEPROM */
289 puts("Board: Freescale MPC837xEMDS\n");
294 int board_pci_host_broken(void)
296 struct immap __iomem
*im
= (struct immap __iomem
*)CONFIG_SYS_IMMR
;
297 const u32 rcw_mask
= HRCWH_PCI1_ARBITER_ENABLE
| HRCWH_PCI_HOST
;
299 /* It's always OK in case of external arbiter. */
300 if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
303 if ((in_be32(&im
->reset
.rcwh
) & rcw_mask
) != rcw_mask
)
309 static void ft_pci_fixup(void *blob
, bd_t
*bd
)
311 const char *status
= "broken (no arbiter)";
315 off
= fdt_path_offset(blob
, "pci0");
317 printf("WARNING: could not find pci0 alias: %s.\n",
322 err
= fdt_setprop(blob
, off
, "status", status
, strlen(status
) + 1);
324 printf("WARNING: could not set status for pci0: %s.\n",
331 #if defined(CONFIG_OF_BOARD_SETUP)
332 void ft_board_setup(void *blob
, bd_t
*bd
)
334 ft_cpu_setup(blob
, bd
);
335 ft_tsec_fixup(blob
, bd
);
336 fdt_fixup_dr_usb(blob
, bd
);
337 fdt_fixup_esdhc(blob
, bd
);
339 ft_pci_setup(blob
, bd
);
340 if (board_pci_host_broken())
341 ft_pci_fixup(blob
, bd
);
342 ft_pcie_fixup(blob
, bd
);
345 #endif /* CONFIG_OF_BOARD_SETUP */