2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/fsl_mpc83xx_serdes.h>
14 #include <fdt_support.h>
15 #include <spd_sdram.h>
17 #include <fsl_esdhc.h>
19 #if defined(CONFIG_SYS_DRAM_TEST)
23 uint
*pstart
= (uint
*) CONFIG_SYS_MEMTEST_START
;
24 uint
*pend
= (uint
*) CONFIG_SYS_MEMTEST_END
;
27 printf("Testing DRAM from 0x%08x to 0x%08x\n",
28 CONFIG_SYS_MEMTEST_START
,
29 CONFIG_SYS_MEMTEST_END
);
31 printf("DRAM test phase 1:\n");
32 for (p
= pstart
; p
< pend
; p
++)
35 for (p
= pstart
; p
< pend
; p
++) {
36 if (*p
!= 0xaaaaaaaa) {
37 printf("DRAM test fails at: %08x\n", (uint
) p
);
42 printf("DRAM test phase 2:\n");
43 for (p
= pstart
; p
< pend
; p
++)
46 for (p
= pstart
; p
< pend
; p
++) {
47 if (*p
!= 0x55555555) {
48 printf("DRAM test fails at: %08x\n", (uint
) p
);
53 printf("DRAM test passed.\n");
58 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
59 void ddr_enable_ecc(unsigned int dram_size
);
61 int fixed_sdram(void);
63 phys_size_t
initdram(int board_type
)
65 immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
68 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
71 #if defined(CONFIG_SPD_EEPROM)
74 msize
= fixed_sdram();
77 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
78 /* Initialize DDR ECC byte */
79 ddr_enable_ecc(msize
* 1024 * 1024);
81 /* return total bus DDR size(bytes) */
82 return (msize
* 1024 * 1024);
85 #if !defined(CONFIG_SPD_EEPROM)
86 /*************************************************************************
87 * fixed sdram init -- doesn't use serial presence detect.
88 ************************************************************************/
91 immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
92 u32 msize
= CONFIG_SYS_DDR_SIZE
* 1024 * 1024;
93 u32 msize_log2
= __ilog2(msize
);
95 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_SDRAM_BASE
& 0xfffff000;
96 im
->sysconf
.ddrlaw
[0].ar
= LBLAWAR_EN
| (msize_log2
- 1);
98 im
->sysconf
.ddrcdr
= CONFIG_SYS_DDRCDR_VALUE
;
101 im
->ddr
.sdram_clk_cntl
= CONFIG_SYS_DDR_SDRAM_CLK_CNTL
;
104 im
->ddr
.csbnds
[0].csbnds
= CONFIG_SYS_DDR_CS0_BNDS
;
105 im
->ddr
.cs_config
[0] = CONFIG_SYS_DDR_CS0_CONFIG
;
108 im
->ddr
.timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
109 im
->ddr
.timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
110 im
->ddr
.timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
111 im
->ddr
.timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
112 im
->ddr
.sdram_cfg
= CONFIG_SYS_DDR_SDRAM_CFG
;
113 im
->ddr
.sdram_cfg2
= CONFIG_SYS_DDR_SDRAM_CFG2
;
114 im
->ddr
.sdram_mode
= CONFIG_SYS_DDR_MODE
;
115 im
->ddr
.sdram_mode2
= CONFIG_SYS_DDR_MODE2
;
116 im
->ddr
.sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
120 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
122 return CONFIG_SYS_DDR_SIZE
;
124 #endif /*!CONFIG_SYS_SPD_EEPROM */
128 puts("Board: Freescale MPC837xERDB\n");
132 int board_early_init_f(void)
134 #ifdef CONFIG_FSL_SERDES
135 immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
136 u32 spridr
= in_be32(&immr
->sysconf
.spridr
);
138 /* we check only part num, and don't look for CPU revisions */
139 switch (PARTID_NO_E(spridr
)) {
141 fsl_setup_serdes(CONFIG_FSL_SERDES1
, FSL_SERDES_PROTO_SATA
,
142 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
143 fsl_setup_serdes(CONFIG_FSL_SERDES2
, FSL_SERDES_PROTO_PEX
,
144 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
147 fsl_setup_serdes(CONFIG_FSL_SERDES2
, FSL_SERDES_PROTO_PEX
,
148 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
151 fsl_setup_serdes(CONFIG_FSL_SERDES1
, FSL_SERDES_PROTO_SATA
,
152 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
153 fsl_setup_serdes(CONFIG_FSL_SERDES2
, FSL_SERDES_PROTO_SATA
,
154 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
157 printf("serdes not configured: unknown CPU part number: "
158 "%04x\n", spridr
>> 16);
161 #endif /* CONFIG_FSL_SERDES */
165 #ifdef CONFIG_FSL_ESDHC
166 int board_mmc_init(bd_t
*bd
)
168 struct immap __iomem
*im
= (struct immap __iomem
*)CONFIG_SYS_IMMR
;
170 if (!hwconfig("esdhc"))
173 clrsetbits_be32(&im
->sysconf
.sicrl
, SICRL_USB_B
, SICRL_USB_B_SD
);
174 clrsetbits_be32(&im
->sysconf
.sicrh
, SICRH_SPI
, SICRH_SPI_SD
);
176 return fsl_esdhc_mmc_init(bd
);
181 * Miscellaneous late-boot configurations
183 * If a VSC7385 microcode image is present, then upload it.
185 int misc_init_r(void)
189 #ifdef CONFIG_VSC7385_IMAGE
190 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE
,
191 CONFIG_VSC7385_IMAGE_SIZE
)) {
192 puts("Failure uploading VSC7385 microcode.\n");
200 #if defined(CONFIG_OF_BOARD_SETUP)
202 void ft_board_setup(void *blob
, bd_t
*bd
)
205 ft_pci_setup(blob
, bd
);
207 ft_cpu_setup(blob
, bd
);
208 fdt_fixup_dr_usb(blob
, bd
);
209 fdt_fixup_esdhc(blob
, bd
);
211 #endif /* CONFIG_OF_BOARD_SETUP */