board/freescale/mpc8536ds/mpc8536ds.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <asm/fsl_serdes.h>
  34 #include <spd.h>
  35 #include <miiphy.h>
  36 #include <libfdt.h>
  37 #include <spd_sdram.h>
  38 #include <fdt_support.h>
  39 #include <tsec.h>
  40 #include <netdev.h>
  41 #include <sata.h>
  42
  43 #include "../common/sgmii_riser.h"
  44
  45 phys_size_t fixed_sdram(void);
  46
  47 int board_early_init_f (void)
  48 {
  49 #ifdef CONFIG_MMC
  50         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  51
  52         setbits_be32(&gur->pmuxcr,
  53                         (MPC85xx_PMUXCR_SD_DATA |
  54                          MPC85xx_PMUXCR_SDHC_CD |
  55                          MPC85xx_PMUXCR_SDHC_WP));
  56
  57 #endif
  58         return 0;
  59 }
  60
  61 int checkboard (void)
  62 {
  63         u8 vboot;
  64         u8 *pixis_base = (u8 *)PIXIS_BASE;
  65
  66         puts("Board: MPC8536DS ");
  67 #ifdef CONFIG_PHYS_64BIT
  68         puts("(36-bit addrmap) ");
  69 #endif
  70
  71         printf ("Sys ID: 0x%02x, "
  72                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  73                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  74                 in_8(pixis_base + PIXIS_PVER));
  75
  76         vboot = in_8(pixis_base + PIXIS_VBOOT);
  77         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
  78                 case PIXIS_VBOOT_LBMAP_NOR0:
  79                         puts ("vBank: 0\n");
  80                         break;
  81                 case PIXIS_VBOOT_LBMAP_NOR1:
  82                         puts ("vBank: 1\n");
  83                         break;
  84                 case PIXIS_VBOOT_LBMAP_NOR2:
  85                         puts ("vBank: 2\n");
  86                         break;
  87                 case PIXIS_VBOOT_LBMAP_NOR3:
  88                         puts ("vBank: 3\n");
  89                         break;
  90                 case PIXIS_VBOOT_LBMAP_PJET:
  91                         puts ("Promjet\n");
  92                         break;
  93                 case PIXIS_VBOOT_LBMAP_NAND:
  94                         puts ("NAND\n");
  95                         break;
  96         }
  97
  98         return 0;
  99 }
 100
 101 phys_size_t
 102 initdram(int board_type)
 103 {
 104         phys_size_t dram_size = 0;
 105
 106         puts("Initializing....");
 107
 108 #ifdef CONFIG_SPD_EEPROM
 109         dram_size = fsl_ddr_sdram();
 110 #else
 111         dram_size = fixed_sdram();
 112 #endif
 113         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 114         dram_size *= 0x100000;
 115
 116         puts("    DDR: ");
 117         return dram_size;
 118 }
 119
 120 #if !defined(CONFIG_SPD_EEPROM)
 121 /*
 122  * Fixed sdram init -- doesn't use serial presence detect.
 123  */
 124
 125 phys_size_t fixed_sdram (void)
 126 {
 127         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 128         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 129         uint d_init;
 130
 131         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 132         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 133
 134         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 135         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 136         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 137         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 138         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 139         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 140         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 141         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 142         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 143         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 144
 145 #if defined (CONFIG_DDR_ECC)
 146         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 147         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 148         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 149 #endif
 150         asm("sync;isync");
 151
 152         udelay(500);
 153
 154         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 155
 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 157         d_init = 1;
 158         debug("DDR - 1st controller: memory initializing\n");
 159         /*
 160          * Poll until memory is initialized.
 161          * 512 Meg at 400 might hit this 200 times or so.
 162          */
 163         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 164                 udelay(1000);
 165         }
 166         debug("DDR: memory initialized\n\n");
 167         asm("sync; isync");
 168         udelay(500);
 169 #endif
 170
 171         return 512 * 1024 * 1024;
 172 }
 173
 174 #endif
 175
 176 #ifdef CONFIG_PCI1
 177 static struct pci_controller pci1_hose;
 178 #endif
 179
 180 #ifdef CONFIG_PCIE1
 181 static struct pci_controller pcie1_hose;
 182 #endif
 183
 184 #ifdef CONFIG_PCIE2
 185 static struct pci_controller pcie2_hose;
 186 #endif
 187
 188 #ifdef CONFIG_PCIE3
 189 static struct pci_controller pcie3_hose;
 190 #endif
 191
 192 #ifdef CONFIG_PCI
 193 void pci_init_board(void)
 194 {
 195         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 196         struct fsl_pci_info pci_info[4];
 197         u32 devdisr, pordevsr, io_sel, sdrs2_io_sel;
 198         u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 199         int first_free_busno = 0;
 200         int num = 0;
 201
 202         int pcie_ep, pcie_configured;
 203
 204         devdisr = in_be32(&gur->devdisr);
 205         pordevsr = in_be32(&gur->pordevsr);
 206         porpllsr = in_be32(&gur->porpllsr);
 207         io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 208         sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
 209
 210         debug("   pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
 211                 devdisr, sdrs2_io_sel, io_sel);
 212
 213         if (sdrs2_io_sel == 7)
 214                 printf("    Serdes2 disalbed\n");
 215         else if (sdrs2_io_sel == 4) {
 216                 printf("    eTSEC1 is in sgmii mode.\n");
 217                 printf("    eTSEC3 is in sgmii mode.\n");
 218         } else if (sdrs2_io_sel == 6)
 219                 printf("    eTSEC1 is in sgmii mode.\n");
 220
 221         puts("\n");
 222 #ifdef CONFIG_PCIE3
 223         pcie_configured = is_serdes_configured(PCIE3);
 224
 225         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 226                 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
 227                                 LAW_TRGT_IF_PCIE_3);
 228                 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
 229                                 LAW_TRGT_IF_PCIE_3);
 230                 SET_STD_PCIE_INFO(pci_info[num], 3);
 231                 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 232                 printf ("    PCIE3 connected to Slot3 as %s (base address %lx)\n",
 233                         pcie_ep ? "Endpoint" : "Root Complex",
 234                         pci_info[num].regs);
 235                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 236                                         &pcie3_hose, first_free_busno);
 237         } else {
 238                 printf ("    PCIE3: disabled\n");
 239         }
 240
 241         puts("\n");
 242 #else
 243         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 244 #endif
 245
 246 #ifdef CONFIG_PCIE1
 247         pcie_configured = is_serdes_configured(PCIE1);
 248
 249         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 250                 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
 251                                 LAW_TRGT_IF_PCIE_1);
 252                 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
 253                                 LAW_TRGT_IF_PCIE_1);
 254                 SET_STD_PCIE_INFO(pci_info[num], 1);
 255                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 256                 printf ("    PCIE1 connected to Slot1 as %s (base address %lx)\n",
 257                         pcie_ep ? "Endpoint" : "Root Complex",
 258                         pci_info[num].regs);
 259                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 260                                         &pcie1_hose, first_free_busno);
 261         } else {
 262                 printf ("    PCIE1: disabled\n");
 263         }
 264
 265         puts("\n");
 266 #else
 267         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 268 #endif
 269
 270 #ifdef CONFIG_PCIE2
 271         pcie_configured = is_serdes_configured(PCIE2);
 272
 273         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 274                 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
 275                                 LAW_TRGT_IF_PCIE_2);
 276                 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
 277                                 LAW_TRGT_IF_PCIE_2);
 278                 SET_STD_PCIE_INFO(pci_info[num], 2);
 279                 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 280                 printf ("    PCIE2 connected to Slot 2 as %s (base address %lx)\n",
 281                         pcie_ep ? "Endpoint" : "Root Complex",
 282                         pci_info[num].regs);
 283                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 284                                         &pcie2_hose, first_free_busno);
 285         } else {
 286                 printf ("    PCIE2: disabled\n");
 287         }
 288
 289         puts("\n");
 290 #else
 291         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
 292 #endif
 293
 294 #ifdef CONFIG_PCI1
 295         pci_speed = 66666000;
 296         pci_32 = 1;
 297         pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 298         pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 299
 300         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 301                 set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
 302                                 LAW_TRGT_IF_PCI);
 303                 set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
 304                                 LAW_TRGT_IF_PCI);
 305                 SET_STD_PCI_INFO(pci_info[num], 1);
 306                 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
 307                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 308                         (pci_32) ? 32 : 64,
 309                         (pci_speed == 33333000) ? "33" :
 310                         (pci_speed == 66666000) ? "66" : "unknown",
 311                         pci_clk_sel ? "sync" : "async",
 312                         pci_agent ? "agent" : "host",
 313                         pci_arb ? "arbiter" : "external-arbiter",
 314                         pci_info[num].regs);
 315
 316                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 317                                         &pci1_hose, first_free_busno);
 318         } else {
 319                 printf ("    PCI: disabled\n");
 320         }
 321
 322         puts("\n");
 323 #else
 324         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 325 #endif
 326 }
 327 #endif
 328
 329 int board_early_init_r(void)
 330 {
 331         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 332         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 333
 334         /*
 335          * Remap Boot flash + PROMJET region to caching-inhibited
 336          * so that flash can be erased properly.
 337          */
 338
 339         /* Flush d-cache and invalidate i-cache of any FLASH data */
 340         flush_dcache();
 341         invalidate_icache();
 342
 343         /* invalidate existing TLB entry for flash + promjet */
 344         disable_tlb(flash_esel);
 345
 346         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 347                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 348                 0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 349
 350         return 0;
 351 }
 352
 353 #ifdef CONFIG_GET_CLK_FROM_ICS307
 354 /* decode S[0-2] to Output Divider (OD) */
 355 static unsigned char
 356 ics307_S_to_OD[] = {
 357         10, 2, 8, 4, 5, 7, 3, 6
 358 };
 359
 360 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 361  * the control bytes being programmed into it. */
 362 /* XXX: This function should probably go into a common library */
 363 static unsigned long
 364 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 365 {
 366         const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 367         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 368         unsigned long RDW = cw2 & 0x7F;
 369         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 370         unsigned long freq;
 371
 372         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 373
 374         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 375          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 376          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 377          *
 378          * R6:R0 = Reference Divider Word (RDW)
 379          * V8:V0 = VCO Divider Word (VDW)
 380          * S2:S0 = Output Divider Select (OD)
 381          * F1:F0 = Function of CLK2 Output
 382          * TTL = duty cycle
 383          * C1:C0 = internal load capacitance for cyrstal
 384          */
 385
 386         /* Adding 1 to get a "nicely" rounded number, but this needs
 387          * more tweaking to get a "properly" rounded number. */
 388
 389         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 390
 391         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 392                 freq);
 393         return freq;
 394 }
 395
 396 unsigned long
 397 get_board_sys_clk(ulong dummy)
 398 {
 399         u8 *pixis_base = (u8 *)PIXIS_BASE;
 400
 401         return ics307_clk_freq (
 402             in_8(pixis_base + PIXIS_VSYSCLK0),
 403             in_8(pixis_base + PIXIS_VSYSCLK1),
 404             in_8(pixis_base + PIXIS_VSYSCLK2)
 405         );
 406 }
 407
 408 unsigned long
 409 get_board_ddr_clk(ulong dummy)
 410 {
 411         u8 *pixis_base = (u8 *)PIXIS_BASE;
 412
 413         return ics307_clk_freq (
 414             in_8(pixis_base + PIXIS_VDDRCLK0),
 415             in_8(pixis_base + PIXIS_VDDRCLK1),
 416             in_8(pixis_base + PIXIS_VDDRCLK2)
 417         );
 418 }
 419 #else
 420 unsigned long
 421 get_board_sys_clk(ulong dummy)
 422 {
 423         u8 i;
 424         ulong val = 0;
 425         u8 *pixis_base = (u8 *)PIXIS_BASE;
 426
 427         i = in_8(pixis_base + PIXIS_SPD);
 428         i &= 0x07;
 429
 430         switch (i) {
 431         case 0:
 432                 val = 33333333;
 433                 break;
 434         case 1:
 435                 val = 40000000;
 436                 break;
 437         case 2:
 438                 val = 50000000;
 439                 break;
 440         case 3:
 441                 val = 66666666;
 442                 break;
 443         case 4:
 444                 val = 83333333;
 445                 break;
 446         case 5:
 447                 val = 100000000;
 448                 break;
 449         case 6:
 450                 val = 133333333;
 451                 break;
 452         case 7:
 453                 val = 166666666;
 454                 break;
 455         }
 456
 457         return val;
 458 }
 459
 460 unsigned long
 461 get_board_ddr_clk(ulong dummy)
 462 {
 463         u8 i;
 464         ulong val = 0;
 465         u8 *pixis_base = (u8 *)PIXIS_BASE;
 466
 467         i = in_8(pixis_base + PIXIS_SPD);
 468         i &= 0x38;
 469         i >>= 3;
 470
 471         switch (i) {
 472         case 0:
 473                 val = 33333333;
 474                 break;
 475         case 1:
 476                 val = 40000000;
 477                 break;
 478         case 2:
 479                 val = 50000000;
 480                 break;
 481         case 3:
 482                 val = 66666666;
 483                 break;
 484         case 4:
 485                 val = 83333333;
 486                 break;
 487         case 5:
 488                 val = 100000000;
 489                 break;
 490         case 6:
 491                 val = 133333333;
 492                 break;
 493         case 7:
 494                 val = 166666666;
 495                 break;
 496         }
 497         return val;
 498 }
 499 #endif
 500
 501 int board_eth_init(bd_t *bis)
 502 {
 503 #ifdef CONFIG_TSEC_ENET
 504         struct tsec_info_struct tsec_info[2];
 505         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 506         int num = 0;
 507         uint sdrs2_io_sel =
 508                 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
 509
 510 #ifdef CONFIG_TSEC1
 511         SET_STD_TSEC_INFO(tsec_info[num], 1);
 512         if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
 513                 tsec_info[num].phyaddr = 0;
 514                 tsec_info[num].flags |= TSEC_SGMII;
 515         }
 516         num++;
 517 #endif
 518 #ifdef CONFIG_TSEC3
 519         SET_STD_TSEC_INFO(tsec_info[num], 3);
 520         if (sdrs2_io_sel == 4) {
 521                 tsec_info[num].phyaddr = 1;
 522                 tsec_info[num].flags |= TSEC_SGMII;
 523         }
 524         num++;
 525 #endif
 526
 527         if (!num) {
 528                 printf("No TSECs initialized\n");
 529                 return 0;
 530         }
 531
 532 #ifdef CONFIG_FSL_SGMII_RISER
 533         if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
 534                 fsl_sgmii_riser_init(tsec_info, num);
 535 #endif
 536
 537         tsec_eth_init(bis, tsec_info, num);
 538 #endif
 539         return pci_eth_init(bis);
 540 }
 541
 542 #if defined(CONFIG_OF_BOARD_SETUP)
 543 void ft_board_setup(void *blob, bd_t *bd)
 544 {
 545         ft_cpu_setup(blob, bd);
 546
 547 #ifdef CONFIG_PCI1
 548         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 549 #else
 550         ft_fsl_pci_setup(blob, "pci0", NULL);
 551 #endif
 552 #ifdef CONFIG_PCIE2
 553         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 554 #else
 555         ft_fsl_pci_setup(blob, "pci1", NULL);
 556 #endif
 557 #ifdef CONFIG_PCIE2
 558         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 559 #else
 560         ft_fsl_pci_setup(blob, "pci2", NULL);
 561 #endif
 562 #ifdef CONFIG_PCIE1
 563         ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
 564 #else
 565         ft_fsl_pci_setup(blob, "pci3", NULL);
 566 #endif
 567 #ifdef CONFIG_FSL_SGMII_RISER
 568         fsl_sgmii_riser_fdt_fixup(blob);
 569 #endif
 570 }
 571 #endif