board/freescale/mpc8536ds/mpc8536ds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <init.h>
   9 #include <net.h>
  10 #include <pci.h>
  11 #include <asm/processor.h>
  12 #include <asm/mmu.h>
  13 #include <asm/cache.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_pci.h>
  16 #include <fsl_ddr_sdram.h>
  17 #include <asm/io.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <spd.h>
  20 #include <miiphy.h>
  21 #include <linux/libfdt.h>
  22 #include <spd_sdram.h>
  23 #include <fdt_support.h>
  24 #include <fsl_mdio.h>
  25 #include <tsec.h>
  26 #include <netdev.h>
  27 #include <sata.h>
  28
  29 #include "../common/sgmii_riser.h"
  30
  31 int board_early_init_f (void)
  32 {
  33 #ifdef CONFIG_MMC
  34         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35
  36         setbits_be32(&gur->pmuxcr,
  37                         (MPC85xx_PMUXCR_SDHC_CD |
  38                          MPC85xx_PMUXCR_SDHC_WP));
  39
  40         /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
  41          * however, this erratum only applies to MPC8536 Rev1.0.
  42          * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
  43         if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
  44                         (SVR_MIN(get_svr()) >= 0x1))
  45                         || (SVR_MAJ(get_svr() & 0x7) > 0x1))
  46                 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
  47 #endif
  48         return 0;
  49 }
  50
  51 int checkboard (void)
  52 {
  53         u8 vboot;
  54         u8 *pixis_base = (u8 *)PIXIS_BASE;
  55
  56         printf("Board: MPC8536DS Sys ID: 0x%02x, "
  57                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  58                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  59                 in_8(pixis_base + PIXIS_PVER));
  60
  61         vboot = in_8(pixis_base + PIXIS_VBOOT);
  62         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
  63                 case PIXIS_VBOOT_LBMAP_NOR0:
  64                         puts ("vBank: 0\n");
  65                         break;
  66                 case PIXIS_VBOOT_LBMAP_NOR1:
  67                         puts ("vBank: 1\n");
  68                         break;
  69                 case PIXIS_VBOOT_LBMAP_NOR2:
  70                         puts ("vBank: 2\n");
  71                         break;
  72                 case PIXIS_VBOOT_LBMAP_NOR3:
  73                         puts ("vBank: 3\n");
  74                         break;
  75                 case PIXIS_VBOOT_LBMAP_PJET:
  76                         puts ("Promjet\n");
  77                         break;
  78                 case PIXIS_VBOOT_LBMAP_NAND:
  79                         puts ("NAND\n");
  80                         break;
  81         }
  82
  83         return 0;
  84 }
  85
  86 #if !defined(CONFIG_SPD_EEPROM)
  87 /*
  88  * Fixed sdram init -- doesn't use serial presence detect.
  89  */
  90
  91 phys_size_t fixed_sdram (void)
  92 {
  93         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  94         struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
  95         uint d_init;
  96
  97         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  98         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  99
 100         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 101         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 102         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 103         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 104         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 105         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 106         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 107         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 108         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 109         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 110
 111 #if defined (CONFIG_DDR_ECC)
 112         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 113         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 114         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 115 #endif
 116         asm("sync;isync");
 117
 118         udelay(500);
 119
 120         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 121
 122 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 123         d_init = 1;
 124         debug("DDR - 1st controller: memory initializing\n");
 125         /*
 126          * Poll until memory is initialized.
 127          * 512 Meg at 400 might hit this 200 times or so.
 128          */
 129         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 130                 udelay(1000);
 131         }
 132         debug("DDR: memory initialized\n\n");
 133         asm("sync; isync");
 134         udelay(500);
 135 #endif
 136
 137         return 512 * 1024 * 1024;
 138 }
 139
 140 #endif
 141
 142 #ifdef CONFIG_PCI1
 143 static struct pci_controller pci1_hose;
 144 #endif
 145
 146 #ifdef CONFIG_PCI
 147 void pci_init_board(void)
 148 {
 149         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 150         struct fsl_pci_info pci_info;
 151         u32 devdisr, pordevsr;
 152         u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 153         int first_free_busno;
 154
 155         first_free_busno = fsl_pcie_init_board(0);
 156
 157 #ifdef CONFIG_PCI1
 158         devdisr = in_be32(&gur->devdisr);
 159         pordevsr = in_be32(&gur->pordevsr);
 160         porpllsr = in_be32(&gur->porpllsr);
 161
 162         pci_speed = 66666000;
 163         pci_32 = 1;
 164         pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 165         pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 166
 167         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 168                 SET_STD_PCI_INFO(pci_info, 1);
 169                 set_next_law(pci_info.mem_phys,
 170                         law_size_bits(pci_info.mem_size), pci_info.law);
 171                 set_next_law(pci_info.io_phys,
 172                         law_size_bits(pci_info.io_size), pci_info.law);
 173
 174                 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 175                 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 176                         (pci_32) ? 32 : 64,
 177                         (pci_speed == 33333000) ? "33" :
 178                         (pci_speed == 66666000) ? "66" : "unknown",
 179                         pci_clk_sel ? "sync" : "async",
 180                         pci_agent ? "agent" : "host",
 181                         pci_arb ? "arbiter" : "external-arbiter",
 182                         pci_info.regs);
 183
 184                 first_free_busno = fsl_pci_init_port(&pci_info,
 185                                         &pci1_hose, first_free_busno);
 186         } else {
 187                 printf("PCI: disabled\n");
 188         }
 189
 190         puts("\n");
 191 #else
 192         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 193 #endif
 194 }
 195 #endif
 196
 197 int board_early_init_r(void)
 198 {
 199         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 200         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 201
 202         /*
 203          * Remap Boot flash + PROMJET region to caching-inhibited
 204          * so that flash can be erased properly.
 205          */
 206
 207         /* Flush d-cache and invalidate i-cache of any FLASH data */
 208         flush_dcache();
 209         invalidate_icache();
 210
 211         if (flash_esel == -1) {
 212                 /* very unlikely unless something is messed up */
 213                 puts("Error: Could not find TLB for FLASH BASE\n");
 214                 flash_esel = 1; /* give our best effort to continue */
 215         } else {
 216                 /* invalidate existing TLB entry for flash + promjet */
 217                 disable_tlb(flash_esel);
 218         }
 219
 220         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 221                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 222                 0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 223
 224         return 0;
 225 }
 226
 227 int board_eth_init(bd_t *bis)
 228 {
 229 #ifdef CONFIG_TSEC_ENET
 230         struct fsl_pq_mdio_info mdio_info;
 231         struct tsec_info_struct tsec_info[2];
 232         int num = 0;
 233
 234 #ifdef CONFIG_TSEC1
 235         SET_STD_TSEC_INFO(tsec_info[num], 1);
 236         if (is_serdes_configured(SGMII_TSEC1)) {
 237                 puts("eTSEC1 is in sgmii mode.\n");
 238                 tsec_info[num].phyaddr = 0;
 239                 tsec_info[num].flags |= TSEC_SGMII;
 240         }
 241         num++;
 242 #endif
 243 #ifdef CONFIG_TSEC3
 244         SET_STD_TSEC_INFO(tsec_info[num], 3);
 245         if (is_serdes_configured(SGMII_TSEC3)) {
 246                 puts("eTSEC3 is in sgmii mode.\n");
 247                 tsec_info[num].phyaddr = 1;
 248                 tsec_info[num].flags |= TSEC_SGMII;
 249         }
 250         num++;
 251 #endif
 252
 253         if (!num) {
 254                 printf("No TSECs initialized\n");
 255                 return 0;
 256         }
 257
 258 #ifdef CONFIG_FSL_SGMII_RISER
 259         if (is_serdes_configured(SGMII_TSEC1) ||
 260             is_serdes_configured(SGMII_TSEC3)) {
 261                 fsl_sgmii_riser_init(tsec_info, num);
 262         }
 263 #endif
 264
 265         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 266         mdio_info.name = DEFAULT_MII_NAME;
 267         fsl_pq_mdio_init(bis, &mdio_info);
 268
 269         tsec_eth_init(bis, tsec_info, num);
 270 #endif
 271         return pci_eth_init(bis);
 272 }
 273
 274 #if defined(CONFIG_OF_BOARD_SETUP)
 275 int ft_board_setup(void *blob, bd_t *bd)
 276 {
 277         ft_cpu_setup(blob, bd);
 278
 279         FT_FSL_PCI_SETUP;
 280
 281 #ifdef CONFIG_FSL_SGMII_RISER
 282         fsl_sgmii_riser_fdt_fixup(blob);
 283 #endif
 284
 285 #ifdef CONFIG_HAS_FSL_MPH_USB
 286         fsl_fdt_fixup_dr_usb(blob, bd);
 287 #endif
 288
 289         return 0;
 290 }
 291 #endif