2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_pci.h>
15 #include <fsl_ddr_sdram.h>
17 #include <asm/fsl_serdes.h>
21 #include <spd_sdram.h>
22 #include <fdt_support.h>
28 #include "../common/sgmii_riser.h"
30 int board_early_init_f (void)
33 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
35 setbits_be32(&gur
->pmuxcr
,
36 (MPC85xx_PMUXCR_SDHC_CD
|
37 MPC85xx_PMUXCR_SDHC_WP
));
39 /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
40 * however, this erratum only applies to MPC8536 Rev1.0.
41 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
42 if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
43 (SVR_MIN(get_svr()) >= 0x1))
44 || (SVR_MAJ(get_svr() & 0x7) > 0x1))
45 setbits_be32(&gur
->gencfgr
, MPC85xx_GENCFGR_SDHC_WP_INV
);
53 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
55 printf("Board: MPC8536DS Sys ID: 0x%02x, "
56 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
57 in_8(pixis_base
+ PIXIS_ID
), in_8(pixis_base
+ PIXIS_VER
),
58 in_8(pixis_base
+ PIXIS_PVER
));
60 vboot
= in_8(pixis_base
+ PIXIS_VBOOT
);
61 switch ((vboot
& PIXIS_VBOOT_LBMAP
) >> 5) {
62 case PIXIS_VBOOT_LBMAP_NOR0
:
65 case PIXIS_VBOOT_LBMAP_NOR1
:
68 case PIXIS_VBOOT_LBMAP_NOR2
:
71 case PIXIS_VBOOT_LBMAP_NOR3
:
74 case PIXIS_VBOOT_LBMAP_PJET
:
77 case PIXIS_VBOOT_LBMAP_NAND
:
85 #if !defined(CONFIG_SPD_EEPROM)
87 * Fixed sdram init -- doesn't use serial presence detect.
90 phys_size_t
fixed_sdram (void)
92 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
93 struct ccsr_ddr __iomem
*ddr
= &immap
->im_ddr
;
96 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
97 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
99 ddr
->timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
100 ddr
->timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
101 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
102 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
103 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE_1
;
104 ddr
->sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
;
105 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
106 ddr
->sdram_data_init
= CONFIG_SYS_DDR_DATA_INIT
;
107 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
;
108 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL2
;
110 #if defined (CONFIG_DDR_ECC)
111 ddr
->err_int_en
= CONFIG_SYS_DDR_ERR_INT_EN
;
112 ddr
->err_disable
= CONFIG_SYS_DDR_ERR_DIS
;
113 ddr
->err_sbe
= CONFIG_SYS_DDR_SBE
;
119 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
121 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
123 debug("DDR - 1st controller: memory initializing\n");
125 * Poll until memory is initialized.
126 * 512 Meg at 400 might hit this 200 times or so.
128 while ((ddr
->sdram_cfg_2
& (d_init
<< 4)) != 0) {
131 debug("DDR: memory initialized\n\n");
136 return 512 * 1024 * 1024;
142 static struct pci_controller pci1_hose
;
146 void pci_init_board(void)
148 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
149 struct fsl_pci_info pci_info
;
150 u32 devdisr
, pordevsr
;
151 u32 porpllsr
, pci_agent
, pci_speed
, pci_32
, pci_arb
, pci_clk_sel
;
152 int first_free_busno
;
154 first_free_busno
= fsl_pcie_init_board(0);
157 devdisr
= in_be32(&gur
->devdisr
);
158 pordevsr
= in_be32(&gur
->pordevsr
);
159 porpllsr
= in_be32(&gur
->porpllsr
);
161 pci_speed
= 66666000;
163 pci_arb
= pordevsr
& MPC85xx_PORDEVSR_PCI1_ARB
;
164 pci_clk_sel
= porpllsr
& MPC85xx_PORDEVSR_PCI1_SPD
;
166 if (!(devdisr
& MPC85xx_DEVDISR_PCI1
)) {
167 SET_STD_PCI_INFO(pci_info
, 1);
168 set_next_law(pci_info
.mem_phys
,
169 law_size_bits(pci_info
.mem_size
), pci_info
.law
);
170 set_next_law(pci_info
.io_phys
,
171 law_size_bits(pci_info
.io_size
), pci_info
.law
);
173 pci_agent
= fsl_setup_hose(&pci1_hose
, pci_info
.regs
);
174 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
176 (pci_speed
== 33333000) ? "33" :
177 (pci_speed
== 66666000) ? "66" : "unknown",
178 pci_clk_sel
? "sync" : "async",
179 pci_agent
? "agent" : "host",
180 pci_arb
? "arbiter" : "external-arbiter",
183 first_free_busno
= fsl_pci_init_port(&pci_info
,
184 &pci1_hose
, first_free_busno
);
186 printf("PCI: disabled\n");
191 setbits_be32(&gur
->devdisr
, MPC85xx_DEVDISR_PCI1
); /* disable */
196 int board_early_init_r(void)
198 const unsigned int flashbase
= CONFIG_SYS_FLASH_BASE
;
199 int flash_esel
= find_tlb_idx((void *)flashbase
, 1);
202 * Remap Boot flash + PROMJET region to caching-inhibited
203 * so that flash can be erased properly.
206 /* Flush d-cache and invalidate i-cache of any FLASH data */
210 if (flash_esel
== -1) {
211 /* very unlikely unless something is messed up */
212 puts("Error: Could not find TLB for FLASH BASE\n");
213 flash_esel
= 1; /* give our best effort to continue */
215 /* invalidate existing TLB entry for flash + promjet */
216 disable_tlb(flash_esel
);
219 set_tlb(1, flashbase
, CONFIG_SYS_FLASH_BASE_PHYS
, /* tlb, epn, rpn */
220 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
, /* perms, wimge */
221 0, flash_esel
, BOOKE_PAGESZ_256M
, 1); /* ts, esel, tsize, iprot */
226 int board_eth_init(bd_t
*bis
)
228 #ifdef CONFIG_TSEC_ENET
229 struct fsl_pq_mdio_info mdio_info
;
230 struct tsec_info_struct tsec_info
[2];
234 SET_STD_TSEC_INFO(tsec_info
[num
], 1);
235 if (is_serdes_configured(SGMII_TSEC1
)) {
236 puts("eTSEC1 is in sgmii mode.\n");
237 tsec_info
[num
].phyaddr
= 0;
238 tsec_info
[num
].flags
|= TSEC_SGMII
;
243 SET_STD_TSEC_INFO(tsec_info
[num
], 3);
244 if (is_serdes_configured(SGMII_TSEC3
)) {
245 puts("eTSEC3 is in sgmii mode.\n");
246 tsec_info
[num
].phyaddr
= 1;
247 tsec_info
[num
].flags
|= TSEC_SGMII
;
253 printf("No TSECs initialized\n");
257 #ifdef CONFIG_FSL_SGMII_RISER
258 if (is_serdes_configured(SGMII_TSEC1
) ||
259 is_serdes_configured(SGMII_TSEC3
)) {
260 fsl_sgmii_riser_init(tsec_info
, num
);
264 mdio_info
.regs
= (struct tsec_mii_mng
*)CONFIG_SYS_MDIO_BASE_ADDR
;
265 mdio_info
.name
= DEFAULT_MII_NAME
;
266 fsl_pq_mdio_init(bis
, &mdio_info
);
268 tsec_eth_init(bis
, tsec_info
, num
);
270 return pci_eth_init(bis
);
273 #if defined(CONFIG_OF_BOARD_SETUP)
274 int ft_board_setup(void *blob
, bd_t
*bd
)
276 ft_cpu_setup(blob
, bd
);
280 #ifdef CONFIG_FSL_SGMII_RISER
281 fsl_sgmii_riser_fdt_fixup(blob
);
284 #ifdef CONFIG_HAS_FSL_MPH_USB
285 fsl_fdt_fixup_dr_usb(blob
, bd
);