board/freescale/mpc8536ds/mpc8536ds.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <pci.h>
  10 #include <asm/processor.h>
  11 #include <asm/mmu.h>
  12 #include <asm/cache.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_pci.h>
  15 #include <fsl_ddr_sdram.h>
  16 #include <asm/io.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <spd.h>
  19 #include <miiphy.h>
  20 #include <libfdt.h>
  21 #include <spd_sdram.h>
  22 #include <fdt_support.h>
  23 #include <fsl_mdio.h>
  24 #include <tsec.h>
  25 #include <netdev.h>
  26 #include <sata.h>
  27
  28 #include "../common/sgmii_riser.h"
  29
  30 int board_early_init_f (void)
  31 {
  32 #ifdef CONFIG_MMC
  33         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  34
  35         setbits_be32(&gur->pmuxcr,
  36                         (MPC85xx_PMUXCR_SDHC_CD |
  37                          MPC85xx_PMUXCR_SDHC_WP));
  38
  39         /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
  40          * however, this erratum only applies to MPC8536 Rev1.0.
  41          * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
  42         if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
  43                         (SVR_MIN(get_svr()) >= 0x1))
  44                         || (SVR_MAJ(get_svr() & 0x7) > 0x1))
  45                 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
  46 #endif
  47         return 0;
  48 }
  49
  50 int checkboard (void)
  51 {
  52         u8 vboot;
  53         u8 *pixis_base = (u8 *)PIXIS_BASE;
  54
  55         printf("Board: MPC8536DS Sys ID: 0x%02x, "
  56                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  57                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  58                 in_8(pixis_base + PIXIS_PVER));
  59
  60         vboot = in_8(pixis_base + PIXIS_VBOOT);
  61         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
  62                 case PIXIS_VBOOT_LBMAP_NOR0:
  63                         puts ("vBank: 0\n");
  64                         break;
  65                 case PIXIS_VBOOT_LBMAP_NOR1:
  66                         puts ("vBank: 1\n");
  67                         break;
  68                 case PIXIS_VBOOT_LBMAP_NOR2:
  69                         puts ("vBank: 2\n");
  70                         break;
  71                 case PIXIS_VBOOT_LBMAP_NOR3:
  72                         puts ("vBank: 3\n");
  73                         break;
  74                 case PIXIS_VBOOT_LBMAP_PJET:
  75                         puts ("Promjet\n");
  76                         break;
  77                 case PIXIS_VBOOT_LBMAP_NAND:
  78                         puts ("NAND\n");
  79                         break;
  80         }
  81
  82         return 0;
  83 }
  84
  85 #if !defined(CONFIG_SPD_EEPROM)
  86 /*
  87  * Fixed sdram init -- doesn't use serial presence detect.
  88  */
  89
  90 phys_size_t fixed_sdram (void)
  91 {
  92         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  93         struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
  94         uint d_init;
  95
  96         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  97         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  98
  99         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 100         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 101         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 102         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 103         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 104         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 105         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 106         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 107         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 108         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 109
 110 #if defined (CONFIG_DDR_ECC)
 111         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 112         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 113         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 114 #endif
 115         asm("sync;isync");
 116
 117         udelay(500);
 118
 119         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 120
 121 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 122         d_init = 1;
 123         debug("DDR - 1st controller: memory initializing\n");
 124         /*
 125          * Poll until memory is initialized.
 126          * 512 Meg at 400 might hit this 200 times or so.
 127          */
 128         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 129                 udelay(1000);
 130         }
 131         debug("DDR: memory initialized\n\n");
 132         asm("sync; isync");
 133         udelay(500);
 134 #endif
 135
 136         return 512 * 1024 * 1024;
 137 }
 138
 139 #endif
 140
 141 #ifdef CONFIG_PCI1
 142 static struct pci_controller pci1_hose;
 143 #endif
 144
 145 #ifdef CONFIG_PCI
 146 void pci_init_board(void)
 147 {
 148         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 149         struct fsl_pci_info pci_info;
 150         u32 devdisr, pordevsr;
 151         u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 152         int first_free_busno;
 153
 154         first_free_busno = fsl_pcie_init_board(0);
 155
 156 #ifdef CONFIG_PCI1
 157         devdisr = in_be32(&gur->devdisr);
 158         pordevsr = in_be32(&gur->pordevsr);
 159         porpllsr = in_be32(&gur->porpllsr);
 160
 161         pci_speed = 66666000;
 162         pci_32 = 1;
 163         pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 164         pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 165
 166         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 167                 SET_STD_PCI_INFO(pci_info, 1);
 168                 set_next_law(pci_info.mem_phys,
 169                         law_size_bits(pci_info.mem_size), pci_info.law);
 170                 set_next_law(pci_info.io_phys,
 171                         law_size_bits(pci_info.io_size), pci_info.law);
 172
 173                 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 174                 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 175                         (pci_32) ? 32 : 64,
 176                         (pci_speed == 33333000) ? "33" :
 177                         (pci_speed == 66666000) ? "66" : "unknown",
 178                         pci_clk_sel ? "sync" : "async",
 179                         pci_agent ? "agent" : "host",
 180                         pci_arb ? "arbiter" : "external-arbiter",
 181                         pci_info.regs);
 182
 183                 first_free_busno = fsl_pci_init_port(&pci_info,
 184                                         &pci1_hose, first_free_busno);
 185         } else {
 186                 printf("PCI: disabled\n");
 187         }
 188
 189         puts("\n");
 190 #else
 191         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 192 #endif
 193 }
 194 #endif
 195
 196 int board_early_init_r(void)
 197 {
 198         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 199         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 200
 201         /*
 202          * Remap Boot flash + PROMJET region to caching-inhibited
 203          * so that flash can be erased properly.
 204          */
 205
 206         /* Flush d-cache and invalidate i-cache of any FLASH data */
 207         flush_dcache();
 208         invalidate_icache();
 209
 210         if (flash_esel == -1) {
 211                 /* very unlikely unless something is messed up */
 212                 puts("Error: Could not find TLB for FLASH BASE\n");
 213                 flash_esel = 1; /* give our best effort to continue */
 214         } else {
 215                 /* invalidate existing TLB entry for flash + promjet */
 216                 disable_tlb(flash_esel);
 217         }
 218
 219         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 220                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 221                 0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 222
 223         return 0;
 224 }
 225
 226 int board_eth_init(bd_t *bis)
 227 {
 228 #ifdef CONFIG_TSEC_ENET
 229         struct fsl_pq_mdio_info mdio_info;
 230         struct tsec_info_struct tsec_info[2];
 231         int num = 0;
 232
 233 #ifdef CONFIG_TSEC1
 234         SET_STD_TSEC_INFO(tsec_info[num], 1);
 235         if (is_serdes_configured(SGMII_TSEC1)) {
 236                 puts("eTSEC1 is in sgmii mode.\n");
 237                 tsec_info[num].phyaddr = 0;
 238                 tsec_info[num].flags |= TSEC_SGMII;
 239         }
 240         num++;
 241 #endif
 242 #ifdef CONFIG_TSEC3
 243         SET_STD_TSEC_INFO(tsec_info[num], 3);
 244         if (is_serdes_configured(SGMII_TSEC3)) {
 245                 puts("eTSEC3 is in sgmii mode.\n");
 246                 tsec_info[num].phyaddr = 1;
 247                 tsec_info[num].flags |= TSEC_SGMII;
 248         }
 249         num++;
 250 #endif
 251
 252         if (!num) {
 253                 printf("No TSECs initialized\n");
 254                 return 0;
 255         }
 256
 257 #ifdef CONFIG_FSL_SGMII_RISER
 258         if (is_serdes_configured(SGMII_TSEC1) ||
 259             is_serdes_configured(SGMII_TSEC3)) {
 260                 fsl_sgmii_riser_init(tsec_info, num);
 261         }
 262 #endif
 263
 264         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 265         mdio_info.name = DEFAULT_MII_NAME;
 266         fsl_pq_mdio_init(bis, &mdio_info);
 267
 268         tsec_eth_init(bis, tsec_info, num);
 269 #endif
 270         return pci_eth_init(bis);
 271 }
 272
 273 #if defined(CONFIG_OF_BOARD_SETUP)
 274 int ft_board_setup(void *blob, bd_t *bd)
 275 {
 276         ft_cpu_setup(blob, bd);
 277
 278         FT_FSL_PCI_SETUP;
 279
 280 #ifdef CONFIG_FSL_SGMII_RISER
 281         fsl_sgmii_riser_fdt_fixup(blob);
 282 #endif
 283
 284 #ifdef CONFIG_HAS_FSL_MPH_USB
 285         fsl_fdt_fixup_dr_usb(blob, bd);
 286 #endif
 287
 288         return 0;
 289 }
 290 #endif