board/freescale/mpc8540ads/mpc8540ads.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003, Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11
  12 #include <common.h>
  13 #include <pci.h>
  14 #include <asm/processor.h>
  15 #include <asm/mmu.h>
  16 #include <asm/immap_85xx.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18 #include <libfdt.h>
  19 #include <fdt_support.h>
  20
  21 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  22 extern void ddr_enable_ecc(unsigned int dram_size);
  23 #endif
  24
  25 void local_bus_init(void);
  26
  27 int checkboard (void)
  28 {
  29         puts("Board: ADS\n");
  30
  31 #ifdef CONFIG_PCI
  32         printf("PCI1: 32 bit, %d MHz (compiled)\n",
  33                CONFIG_SYS_CLK_FREQ / 1000000);
  34 #else
  35         printf("PCI1: disabled\n");
  36 #endif
  37
  38         /*
  39          * Initialize local bus.
  40          */
  41         local_bus_init();
  42
  43         return 0;
  44 }
  45
  46 /*
  47  * Initialize Local Bus
  48  */
  49
  50 void
  51 local_bus_init(void)
  52 {
  53         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  54         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  55
  56         uint clkdiv;
  57         uint lbc_hz;
  58         sys_info_t sysinfo;
  59
  60         /*
  61          * Errata LBC11.
  62          * Fix Local Bus clock glitch when DLL is enabled.
  63          *
  64          * If localbus freq is < 66MHz, DLL bypass mode must be used.
  65          * If localbus freq is > 133MHz, DLL can be safely enabled.
  66          * Between 66 and 133, the DLL is enabled with an override workaround.
  67          */
  68
  69         get_sys_info(&sysinfo);
  70         clkdiv = lbc->lcrr & LCRR_CLKDIV;
  71         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
  72
  73         if (lbc_hz < 66) {
  74                 lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;    /* DLL Bypass */
  75
  76         } else if (lbc_hz >= 133) {
  77                 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
  78
  79         } else {
  80                 /*
  81                  * On REV1 boards, need to change CLKDIV before enable DLL.
  82                  * Default CLKDIV is 8, change it to 4 temporarily.
  83                  */
  84                 uint pvr = get_pvr();
  85                 uint temp_lbcdll = 0;
  86
  87                 if (pvr == PVR_85xx_REV1) {
  88                         /* FIXME: Justify the high bit here. */
  89                         lbc->lcrr = 0x10000004;
  90                 }
  91
  92                 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
  93                 udelay(200);
  94
  95                 /*
  96                  * Sample LBC DLL ctrl reg, upshift it to set the
  97                  * override bits.
  98                  */
  99                 temp_lbcdll = gur->lbcdllcr;
 100                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 101                 asm("sync;isync;msync");
 102         }
 103 }
 104
 105
 106 /*
 107  * Initialize SDRAM memory on the Local Bus.
 108  */
 109 void lbc_sdram_init(void)
 110 {
 111         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 112         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 113
 114         puts("LBC SDRAM: ");
 115         print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 116                    "\n       ");
 117
 118         /*
 119          * Setup SDRAM Base and Option Registers
 120          */
 121         set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 122         set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 123         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 124         asm("msync");
 125
 126         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 127         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 128         asm("sync");
 129
 130         /*
 131          * Configure the SDRAM controller.
 132          */
 133         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 134         asm("sync");
 135         *sdram_addr = 0xff;
 136         ppcDcbf((unsigned long) sdram_addr);
 137         udelay(100);
 138
 139         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 140         asm("sync");
 141         *sdram_addr = 0xff;
 142         ppcDcbf((unsigned long) sdram_addr);
 143         udelay(100);
 144
 145         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 146         asm("sync");
 147         *sdram_addr = 0xff;
 148         ppcDcbf((unsigned long) sdram_addr);
 149         udelay(100);
 150
 151         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 152         asm("sync");
 153         *sdram_addr = 0xff;
 154         ppcDcbf((unsigned long) sdram_addr);
 155         udelay(100);
 156
 157         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 158         asm("sync");
 159         *sdram_addr = 0xff;
 160         ppcDcbf((unsigned long) sdram_addr);
 161         udelay(100);
 162 }
 163
 164 #if !defined(CONFIG_SPD_EEPROM)
 165 /*************************************************************************
 166  *  fixed sdram init -- doesn't use serial presence detect.
 167  ************************************************************************/
 168 phys_size_t fixed_sdram(void)
 169 {
 170   #ifndef CONFIG_SYS_RAMBOOT
 171         volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 172
 173         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 174         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 175         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 176         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 177         ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
 178         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 179     #if defined (CONFIG_DDR_ECC)
 180         ddr->err_disable = 0x0000000D;
 181         ddr->err_sbe = 0x00ff0000;
 182     #endif
 183         asm("sync;isync;msync");
 184         udelay(500);
 185     #if defined (CONFIG_DDR_ECC)
 186         /* Enable ECC checking */
 187         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 188     #else
 189         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 190     #endif
 191         asm("sync; isync; msync");
 192         udelay(500);
 193   #endif
 194         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 195 }
 196 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 197
 198
 199 #if defined(CONFIG_PCI)
 200 /*
 201  * Initialize PCI Devices, report devices found.
 202  */
 203
 204
 205 static struct pci_controller hose;
 206
 207 #endif  /* CONFIG_PCI */
 208
 209
 210 void
 211 pci_init_board(void)
 212 {
 213 #ifdef CONFIG_PCI
 214         pci_mpc85xx_init(&hose);
 215 #endif /* CONFIG_PCI */
 216 }
 217
 218
 219 #if defined(CONFIG_OF_BOARD_SETUP)
 220 void
 221 ft_board_setup(void *blob, bd_t *bd)
 222 {
 223         int node, tmp[2];
 224         const char *path;
 225
 226         ft_cpu_setup(blob, bd);
 227
 228         node = fdt_path_offset(blob, "/aliases");
 229         tmp[0] = 0;
 230         if (node >= 0) {
 231 #ifdef CONFIG_PCI
 232                 path = fdt_getprop(blob, node, "pci0", NULL);
 233                 if (path) {
 234                         tmp[1] = hose.last_busno - hose.first_busno;
 235                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 236                 }
 237 #endif
 238         }
 239 }
 240 #endif