2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38 extern void ddr_enable_ecc(unsigned int dram_size
);
41 void local_bus_init(void);
42 void sdram_init(void);
43 long int fixed_sdram(void);
50 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
51 CONFIG_SYS_CLK_FREQ
/ 1000000);
53 printf(" PCI1: disabled\n");
57 * Initialize local bus.
66 initdram(int board_type
)
70 puts("Initializing\n");
72 #if defined(CONFIG_DDR_DLL)
74 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
78 * Work around to stabilize DDR DLL
80 temp_ddrdll
= gur
->ddrdllcr
;
81 gur
->ddrdllcr
= ((temp_ddrdll
& 0xff) << 16) | 0x80000000;
82 asm("sync;isync;msync");
86 #ifdef CONFIG_SPD_EEPROM
87 dram_size
= fsl_ddr_sdram();
88 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
90 dram_size
*= 0x100000;
92 dram_size
= fixed_sdram();
95 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
97 * Initialize and enable DDR ECC.
99 ddr_enable_ecc(dram_size
);
113 * Initialize Local Bus
119 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
120 volatile ccsr_lbc_t
*lbc
= (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR
);
128 * Fix Local Bus clock glitch when DLL is enabled.
130 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
131 * If localbus freq is > 133Mhz, DLL can be safely enabled.
132 * Between 66 and 133, the DLL is enabled with an override workaround.
135 get_sys_info(&sysinfo
);
136 clkdiv
= lbc
->lcrr
& 0x0f;
137 lbc_hz
= sysinfo
.freqSystemBus
/ 1000000 / clkdiv
;
140 lbc
->lcrr
= CONFIG_SYS_LBC_LCRR
| 0x80000000; /* DLL Bypass */
142 } else if (lbc_hz
>= 133) {
143 lbc
->lcrr
= CONFIG_SYS_LBC_LCRR
& (~0x80000000); /* DLL Enabled */
147 * On REV1 boards, need to change CLKDIV before enable DLL.
148 * Default CLKDIV is 8, change it to 4 temporarily.
150 uint pvr
= get_pvr();
151 uint temp_lbcdll
= 0;
153 if (pvr
== PVR_85xx_REV1
) {
154 /* FIXME: Justify the high bit here. */
155 lbc
->lcrr
= 0x10000004;
158 lbc
->lcrr
= CONFIG_SYS_LBC_LCRR
& (~0x80000000); /* DLL Enabled */
162 * Sample LBC DLL ctrl reg, upshift it to set the
165 temp_lbcdll
= gur
->lbcdllcr
;
166 gur
->lbcdllcr
= (((temp_lbcdll
& 0xff) << 16) | 0x80000000);
167 asm("sync;isync;msync");
173 * Initialize SDRAM memory on the Local Bus.
179 volatile ccsr_lbc_t
*lbc
= (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR
);
180 uint
*sdram_addr
= (uint
*)CONFIG_SYS_LBC_SDRAM_BASE
;
183 print_size (CONFIG_SYS_LBC_SDRAM_SIZE
* 1024 * 1024, "\n");
186 * Setup SDRAM Base and Option Registers
188 lbc
->or2
= CONFIG_SYS_OR2_PRELIM
;
189 lbc
->br2
= CONFIG_SYS_BR2_PRELIM
;
190 lbc
->lbcr
= CONFIG_SYS_LBC_LBCR
;
193 lbc
->lsrt
= CONFIG_SYS_LBC_LSRT
;
194 lbc
->mrtpr
= CONFIG_SYS_LBC_MRTPR
;
198 * Configure the SDRAM controller.
200 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_1
;
203 ppcDcbf((unsigned long) sdram_addr
);
206 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_2
;
209 ppcDcbf((unsigned long) sdram_addr
);
212 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_3
;
215 ppcDcbf((unsigned long) sdram_addr
);
218 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_4
;
221 ppcDcbf((unsigned long) sdram_addr
);
224 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_5
;
227 ppcDcbf((unsigned long) sdram_addr
);
231 #if !defined(CONFIG_SPD_EEPROM)
232 /*************************************************************************
233 * fixed sdram init -- doesn't use serial presence detect.
234 ************************************************************************/
235 long int fixed_sdram (void)
237 #ifndef CONFIG_SYS_RAMBOOT
238 volatile ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR
);
240 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
241 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
242 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
243 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
244 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE
;
245 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
246 #if defined (CONFIG_DDR_ECC)
247 ddr
->err_disable
= 0x0000000D;
248 ddr
->err_sbe
= 0x00ff0000;
250 asm("sync;isync;msync");
252 #if defined (CONFIG_DDR_ECC)
253 /* Enable ECC checking */
254 ddr
->sdram_cfg
= (CONFIG_SYS_DDR_CONTROL
| 0x20000000);
256 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
258 asm("sync; isync; msync");
261 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
263 #endif /* !defined(CONFIG_SPD_EEPROM) */
266 #if defined(CONFIG_PCI)
268 * Initialize PCI Devices, report devices found.
272 static struct pci_controller hose
;
274 #endif /* CONFIG_PCI */
281 pci_mpc85xx_init(&hose
);
282 #endif /* CONFIG_PCI */
286 #if defined(CONFIG_OF_BOARD_SETUP)
288 ft_board_setup(void *blob
, bd_t
*bd
)
293 ft_cpu_setup(blob
, bd
);
295 node
= fdt_path_offset(blob
, "/aliases");
299 path
= fdt_getprop(blob
, node
, "pci0", NULL
);
301 tmp
[1] = hose
.last_busno
- hose
.first_busno
;
302 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);