2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
43 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
44 volatile ccsr_lbc_t
*lbc
= (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR
);
45 volatile ccsr_local_ecm_t
*ecm
= (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR
);
47 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
49 if ((uint
)&gur
->porpllsr
!= 0xe00e0000) {
50 printf("immap size error %lx\n",(ulong
)&gur
->porpllsr
);
52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
54 in_8(pixis_base
+ PIXIS_ID
), in_8(pixis_base
+ PIXIS_VER
),
55 in_8(pixis_base
+ PIXIS_PVER
));
57 vboot
= in_8(pixis_base
+ PIXIS_VBOOT
);
58 if (vboot
& PIXIS_VBOOT_FMAP
)
59 printf ("vBank: %d\n", ((vboot
& PIXIS_VBOOT_FBANK
) >> 6));
63 lbc
->ltesr
= 0xffffffff; /* Clear LBC error interrupts */
64 lbc
->lteir
= 0xffffffff; /* Enable LBC error interrupts */
65 ecm
->eedr
= 0xffffffff; /* Clear ecm errors */
66 ecm
->eeer
= 0xffffffff; /* Enable ecm errors */
72 initdram(int board_type
)
76 puts("Initializing\n");
78 dram_size
= fsl_ddr_sdram();
80 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
82 dram_size
*= 0x100000;
89 static struct pci_controller pci1_hose
;
93 static struct pci_controller pcie1_hose
;
97 static struct pci_controller pcie2_hose
;
101 static struct pci_controller pcie3_hose
;
104 int first_free_busno
=0;
109 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
110 uint devdisr
= gur
->devdisr
;
111 uint io_sel
= (gur
->pordevsr
& MPC85xx_PORDEVSR_IO_SEL
) >> 19;
112 uint host_agent
= (gur
->porbmsr
& MPC85xx_PORBMSR_HA
) >> 16;
114 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
115 devdisr
, io_sel
, host_agent
);
118 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII1_DIS
))
119 printf (" eTSEC1 is in sgmii mode.\n");
120 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
121 printf (" eTSEC3 is in sgmii mode.\n");
126 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE3_ADDR
;
127 struct pci_controller
*hose
= &pcie3_hose
;
128 int pcie_ep
= is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3
, host_agent
);
129 int pcie_configured
= is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3
, io_sel
);
130 struct pci_region
*r
= hose
->regions
;
132 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
133 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
134 pcie_ep
? "End Point" : "Root Complex",
136 if (pci
->pme_msg_det
) {
137 pci
->pme_msg_det
= 0xffffffff;
138 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
142 /* outbound memory */
144 CONFIG_SYS_PCIE3_MEM_BUS
,
145 CONFIG_SYS_PCIE3_MEM_PHYS
,
146 CONFIG_SYS_PCIE3_MEM_SIZE
,
151 CONFIG_SYS_PCIE3_IO_BUS
,
152 CONFIG_SYS_PCIE3_IO_PHYS
,
153 CONFIG_SYS_PCIE3_IO_SIZE
,
156 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
157 /* outbound memory */
159 CONFIG_SYS_PCIE3_MEM_BUS2
,
160 CONFIG_SYS_PCIE3_MEM_PHYS2
,
161 CONFIG_SYS_PCIE3_MEM_SIZE2
,
164 hose
->region_count
= r
- hose
->regions
;
165 hose
->first_busno
=first_free_busno
;
167 fsl_pci_init(hose
, (u32
)&pci
->cfg_addr
, (u32
)&pci
->cfg_data
);
169 first_free_busno
=hose
->last_busno
+1;
170 printf (" PCIE3 on bus %02x - %02x\n",
171 hose
->first_busno
,hose
->last_busno
);
174 * Activate ULI1575 legacy chip by performing a fake
175 * memory access. Needed to make ULI RTC work.
177 in_be32((u32
*)CONFIG_SYS_PCIE3_MEM_BUS
);
179 printf (" PCIE3: disabled\n");
184 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE3
; /* disable */
189 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE1_ADDR
;
190 struct pci_controller
*hose
= &pcie1_hose
;
191 int pcie_ep
= is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1
, host_agent
);
192 int pcie_configured
= is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1
, io_sel
);
193 struct pci_region
*r
= hose
->regions
;
195 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
196 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
197 pcie_ep
? "End Point" : "Root Complex",
199 if (pci
->pme_msg_det
) {
200 pci
->pme_msg_det
= 0xffffffff;
201 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
205 /* outbound memory */
207 CONFIG_SYS_PCIE1_MEM_BUS
,
208 CONFIG_SYS_PCIE1_MEM_PHYS
,
209 CONFIG_SYS_PCIE1_MEM_SIZE
,
214 CONFIG_SYS_PCIE1_IO_BUS
,
215 CONFIG_SYS_PCIE1_IO_PHYS
,
216 CONFIG_SYS_PCIE1_IO_SIZE
,
219 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
220 /* outbound memory */
222 CONFIG_SYS_PCIE1_MEM_BUS2
,
223 CONFIG_SYS_PCIE1_MEM_PHYS2
,
224 CONFIG_SYS_PCIE1_MEM_SIZE2
,
227 hose
->region_count
= r
- hose
->regions
;
228 hose
->first_busno
=first_free_busno
;
230 fsl_pci_init(hose
, (u32
)&pci
->cfg_addr
, (u32
)&pci
->cfg_data
);
232 first_free_busno
=hose
->last_busno
+1;
233 printf(" PCIE1 on bus %02x - %02x\n",
234 hose
->first_busno
,hose
->last_busno
);
237 printf (" PCIE1: disabled\n");
242 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE
; /* disable */
247 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE2_ADDR
;
248 struct pci_controller
*hose
= &pcie2_hose
;
249 int pcie_ep
= is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2
, host_agent
);
250 int pcie_configured
= is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2
, io_sel
);
251 struct pci_region
*r
= hose
->regions
;
253 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
254 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
255 pcie_ep
? "End Point" : "Root Complex",
257 if (pci
->pme_msg_det
) {
258 pci
->pme_msg_det
= 0xffffffff;
259 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
263 /* outbound memory */
265 CONFIG_SYS_PCIE2_MEM_BUS
,
266 CONFIG_SYS_PCIE2_MEM_PHYS
,
267 CONFIG_SYS_PCIE2_MEM_SIZE
,
272 CONFIG_SYS_PCIE2_IO_BUS
,
273 CONFIG_SYS_PCIE2_IO_PHYS
,
274 CONFIG_SYS_PCIE2_IO_SIZE
,
277 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
278 /* outbound memory */
280 CONFIG_SYS_PCIE2_MEM_BUS2
,
281 CONFIG_SYS_PCIE2_MEM_PHYS2
,
282 CONFIG_SYS_PCIE2_MEM_SIZE2
,
285 hose
->region_count
= r
- hose
->regions
;
286 hose
->first_busno
=first_free_busno
;
288 fsl_pci_init(hose
, (u32
)&pci
->cfg_addr
, (u32
)&pci
->cfg_data
);
289 first_free_busno
=hose
->last_busno
+1;
290 printf (" PCIE2 on bus %02x - %02x\n",
291 hose
->first_busno
,hose
->last_busno
);
294 printf (" PCIE2: disabled\n");
299 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE2
; /* disable */
305 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCI1_ADDR
;
306 struct pci_controller
*hose
= &pci1_hose
;
307 struct pci_region
*r
= hose
->regions
;
309 uint pci_agent
= is_fsl_pci_agent(LAW_TRGT_IF_PCI
, host_agent
);
310 uint pci_speed
= 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
312 uint pci_arb
= gur
->pordevsr
& MPC85xx_PORDEVSR_PCI1_ARB
; /* PORDEVSR[14] */
313 uint pci_clk_sel
= gur
->porpllsr
& MPC85xx_PORDEVSR_PCI1_SPD
; /* PORPLLSR[16] */
316 if (!(devdisr
& MPC85xx_DEVDISR_PCI1
)) {
317 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
319 (pci_speed
== 33333000) ? "33" :
320 (pci_speed
== 66666000) ? "66" : "unknown",
321 pci_clk_sel
? "sync" : "async",
322 pci_agent
? "agent" : "host",
323 pci_arb
? "arbiter" : "external-arbiter",
327 /* outbound memory */
329 CONFIG_SYS_PCI1_MEM_BUS
,
330 CONFIG_SYS_PCI1_MEM_PHYS
,
331 CONFIG_SYS_PCI1_MEM_SIZE
,
336 CONFIG_SYS_PCI1_IO_BUS
,
337 CONFIG_SYS_PCI1_IO_PHYS
,
338 CONFIG_SYS_PCI1_IO_SIZE
,
341 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
342 /* outbound memory */
344 CONFIG_SYS_PCIE3_MEM_BUS2
,
345 CONFIG_SYS_PCIE3_MEM_PHYS2
,
346 CONFIG_SYS_PCIE3_MEM_SIZE2
,
349 hose
->region_count
= r
- hose
->regions
;
350 hose
->first_busno
=first_free_busno
;
352 fsl_pci_init(hose
, (u32
)&pci
->cfg_addr
, (u32
)&pci
->cfg_data
);
353 first_free_busno
=hose
->last_busno
+1;
354 printf ("PCI on bus %02x - %02x\n",
355 hose
->first_busno
,hose
->last_busno
);
357 printf (" PCI: disabled\n");
361 gur
->devdisr
|= MPC85xx_DEVDISR_PCI1
; /* disable */
366 int last_stage_init(void)
373 get_board_sys_clk(ulong dummy
)
375 u8 i
, go_bit
, rd_clks
;
377 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
379 go_bit
= in_8(pixis_base
+ PIXIS_VCTL
);
382 rd_clks
= in_8(pixis_base
+ PIXIS_VCFGEN0
);
386 * Only if both go bit and the SCLK bit in VCFGEN0 are set
387 * should we be using the AUX register. Remember, we also set the
388 * GO bit to boot from the alternate bank on the on-board flash
393 i
= in_8(pixis_base
+ PIXIS_AUX
);
395 i
= in_8(pixis_base
+ PIXIS_SPD
);
397 i
= in_8(pixis_base
+ PIXIS_SPD
);
432 int board_eth_init(bd_t
*bis
)
434 #ifdef CONFIG_TSEC_ENET
435 struct tsec_info_struct tsec_info
[2];
436 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
437 uint io_sel
= (gur
->pordevsr
& MPC85xx_PORDEVSR_IO_SEL
) >> 19;
441 SET_STD_TSEC_INFO(tsec_info
[num
], 1);
442 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII1_DIS
))
443 tsec_info
[num
].flags
|= TSEC_SGMII
;
447 SET_STD_TSEC_INFO(tsec_info
[num
], 3);
448 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
449 tsec_info
[num
].flags
|= TSEC_SGMII
;
454 printf("No TSECs initialized\n");
460 fsl_sgmii_riser_init(tsec_info
, num
);
463 tsec_eth_init(bis
, tsec_info
, num
);
465 return pci_eth_init(bis
);
468 #if defined(CONFIG_OF_BOARD_SETUP)
469 void ft_board_setup(void *blob
, bd_t
*bd
)
471 ft_cpu_setup(blob
, bd
);
475 ft_fsl_pci_setup(blob
, "pci0", &pci1_hose
);
478 ft_fsl_pci_setup(blob
, "pci1", &pcie1_hose
);
481 ft_fsl_pci_setup(blob
, "pci2", &pcie3_hose
);
484 ft_fsl_pci_setup(blob
, "pci3", &pcie2_hose
);
486 #ifdef CONFIG_FSL_SGMII_RISER
487 fsl_sgmii_riser_fdt_fixup(blob
);