board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_85xx.h>
  28 #include <asm/immap_fsl_pci.h>
  29 #include <asm/io.h>
  30 #include <spd.h>
  31 #include <miiphy.h>
  32 #include <libfdt.h>
  33 #include <fdt_support.h>
  34
  35 #include "../common/pixis.h"
  36
  37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  38 extern void ddr_enable_ecc(unsigned int dram_size);
  39 #endif
  40
  41 extern long int spd_sdram(void);
  42
  43 void sdram_init(void);
  44
  45 int board_early_init_f (void)
  46 {
  47         return 0;
  48 }
  49
  50 int checkboard (void)
  51 {
  52         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  53         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  54         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
  55
  56         if ((uint)&gur->porpllsr != 0xe00e0000) {
  57                 printf("immap size error %x\n",&gur->porpllsr);
  58         }
  59         printf ("Board: MPC8544DS\n");
  60
  61         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  62         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  63         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  64         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  65
  66         return 0;
  67 }
  68
  69 long int
  70 initdram(int board_type)
  71 {
  72         long dram_size = 0;
  73
  74         puts("Initializing\n");
  75
  76         dram_size = spd_sdram();
  77
  78 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  79         /*
  80          * Initialize and enable DDR ECC.
  81          */
  82         ddr_enable_ecc(dram_size);
  83 #endif
  84         puts("    DDR: ");
  85         return dram_size;
  86 }
  87
  88 #if defined(CFG_DRAM_TEST)
  89 int
  90 testdram(void)
  91 {
  92         uint *pstart = (uint *) CFG_MEMTEST_START;
  93         uint *pend = (uint *) CFG_MEMTEST_END;
  94         uint *p;
  95
  96         printf("Testing DRAM from 0x%08x to 0x%08x\n",
  97                CFG_MEMTEST_START,
  98                CFG_MEMTEST_END);
  99
 100         printf("DRAM test phase 1:\n");
 101         for (p = pstart; p < pend; p++)
 102                 *p = 0xaaaaaaaa;
 103
 104         for (p = pstart; p < pend; p++) {
 105                 if (*p != 0xaaaaaaaa) {
 106                         printf ("DRAM test fails at: %08x\n", (uint) p);
 107                         return 1;
 108                 }
 109         }
 110
 111         printf("DRAM test phase 2:\n");
 112         for (p = pstart; p < pend; p++)
 113                 *p = 0x55555555;
 114
 115         for (p = pstart; p < pend; p++) {
 116                 if (*p != 0x55555555) {
 117                         printf ("DRAM test fails at: %08x\n", (uint) p);
 118                         return 1;
 119                 }
 120         }
 121
 122         printf("DRAM test passed.\n");
 123         return 0;
 124 }
 125 #endif
 126
 127 #ifdef CONFIG_PCI1
 128 static struct pci_controller pci1_hose;
 129 #endif
 130
 131 #ifdef CONFIG_PCIE1
 132 static struct pci_controller pcie1_hose;
 133 #endif
 134
 135 #ifdef CONFIG_PCIE2
 136 static struct pci_controller pcie2_hose;
 137 #endif
 138
 139 #ifdef CONFIG_PCIE3
 140 static struct pci_controller pcie3_hose;
 141 #endif
 142
 143 int first_free_busno=0;
 144
 145 void
 146 pci_init_board(void)
 147 {
 148         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 149         uint devdisr = gur->devdisr;
 150         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 151         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 152
 153         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 154                 devdisr, io_sel, host_agent);
 155
 156         if (io_sel & 1) {
 157                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 158                         printf ("    eTSEC1 is in sgmii mode.\n");
 159                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 160                         printf ("    eTSEC3 is in sgmii mode.\n");
 161         }
 162
 163 #ifdef CONFIG_PCIE3
 164 {
 165         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
 166         extern void fsl_pci_init(struct pci_controller *hose);
 167         struct pci_controller *hose = &pcie3_hose;
 168         int pcie_ep = (host_agent == 3);
 169         int pcie_configured  = io_sel >= 1;
 170
 171         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 172                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 173                         pcie_ep ? "End Point" : "Root Complex",
 174                         (uint)pci);
 175                 if (pci->pme_msg_det) {
 176                         pci->pme_msg_det = 0xffffffff;
 177                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 178                 }
 179                 printf ("\n");
 180
 181                 /* inbound */
 182                 pci_set_region(hose->regions + 0,
 183                                CFG_PCI_MEMORY_BUS,
 184                                CFG_PCI_MEMORY_PHYS,
 185                                CFG_PCI_MEMORY_SIZE,
 186                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 187
 188                 /* outbound memory */
 189                 pci_set_region(hose->regions + 1,
 190                                CFG_PCIE3_MEM_BASE,
 191                                CFG_PCIE3_MEM_PHYS,
 192                                CFG_PCIE3_MEM_SIZE,
 193                                PCI_REGION_MEM);
 194
 195                 /* outbound io */
 196                 pci_set_region(hose->regions + 2,
 197                                CFG_PCIE3_IO_BASE,
 198                                CFG_PCIE3_IO_PHYS,
 199                                CFG_PCIE3_IO_SIZE,
 200                                PCI_REGION_IO);
 201
 202                 hose->region_count = 3;
 203 #ifdef CFG_PCIE3_MEM_BASE2
 204                 /* outbound memory */
 205                 pci_set_region(hose->regions + 3,
 206                                CFG_PCIE3_MEM_BASE2,
 207                                CFG_PCIE3_MEM_PHYS2,
 208                                CFG_PCIE3_MEM_SIZE2,
 209                                PCI_REGION_MEM);
 210                 hose->region_count++;
 211 #endif
 212                 hose->first_busno=first_free_busno;
 213                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 214
 215                 fsl_pci_init(hose);
 216
 217                 first_free_busno=hose->last_busno+1;
 218                 printf ("    PCIE3 on bus %02x - %02x\n",
 219                         hose->first_busno,hose->last_busno);
 220
 221                 /*
 222                  * Activate ULI1575 legacy chip by performing a fake
 223                  * memory access.  Needed to make ULI RTC work.
 224                  */
 225                 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
 226         } else {
 227                 printf ("    PCIE3: disabled\n");
 228         }
 229
 230  }
 231 #else
 232         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 233 #endif
 234
 235 #ifdef CONFIG_PCIE1
 236  {
 237         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 238         extern void fsl_pci_init(struct pci_controller *hose);
 239         struct pci_controller *hose = &pcie1_hose;
 240         int pcie_ep = (host_agent == 5);
 241         int pcie_configured  = io_sel & 6;
 242
 243         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 244                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 245                         pcie_ep ? "End Point" : "Root Complex",
 246                         (uint)pci);
 247                 if (pci->pme_msg_det) {
 248                         pci->pme_msg_det = 0xffffffff;
 249                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 250                 }
 251                 printf ("\n");
 252
 253                 /* inbound */
 254                 pci_set_region(hose->regions + 0,
 255                                CFG_PCI_MEMORY_BUS,
 256                                CFG_PCI_MEMORY_PHYS,
 257                                CFG_PCI_MEMORY_SIZE,
 258                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 259
 260                 /* outbound memory */
 261                 pci_set_region(hose->regions + 1,
 262                                CFG_PCIE1_MEM_BASE,
 263                                CFG_PCIE1_MEM_PHYS,
 264                                CFG_PCIE1_MEM_SIZE,
 265                                PCI_REGION_MEM);
 266
 267                 /* outbound io */
 268                 pci_set_region(hose->regions + 2,
 269                                CFG_PCIE1_IO_BASE,
 270                                CFG_PCIE1_IO_PHYS,
 271                                CFG_PCIE1_IO_SIZE,
 272                                PCI_REGION_IO);
 273
 274                 hose->region_count = 3;
 275 #ifdef CFG_PCIE1_MEM_BASE2
 276                 /* outbound memory */
 277                 pci_set_region(hose->regions + 3,
 278                                CFG_PCIE1_MEM_BASE2,
 279                                CFG_PCIE1_MEM_PHYS2,
 280                                CFG_PCIE1_MEM_SIZE2,
 281                                PCI_REGION_MEM);
 282                 hose->region_count++;
 283 #endif
 284                 hose->first_busno=first_free_busno;
 285
 286                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 287
 288                 fsl_pci_init(hose);
 289
 290                 first_free_busno=hose->last_busno+1;
 291                 printf("    PCIE1 on bus %02x - %02x\n",
 292                        hose->first_busno,hose->last_busno);
 293
 294         } else {
 295                 printf ("    PCIE1: disabled\n");
 296         }
 297
 298  }
 299 #else
 300         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 301 #endif
 302
 303 #ifdef CONFIG_PCIE2
 304  {
 305         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 306         extern void fsl_pci_init(struct pci_controller *hose);
 307         struct pci_controller *hose = &pcie2_hose;
 308         int pcie_ep = (host_agent == 3);
 309         int pcie_configured  = io_sel & 4;
 310
 311         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 312                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 313                         pcie_ep ? "End Point" : "Root Complex",
 314                         (uint)pci);
 315                 if (pci->pme_msg_det) {
 316                         pci->pme_msg_det = 0xffffffff;
 317                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 318                 }
 319                 printf ("\n");
 320
 321                 /* inbound */
 322                 pci_set_region(hose->regions + 0,
 323                                CFG_PCI_MEMORY_BUS,
 324                                CFG_PCI_MEMORY_PHYS,
 325                                CFG_PCI_MEMORY_SIZE,
 326                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 327
 328                 /* outbound memory */
 329                 pci_set_region(hose->regions + 1,
 330                                CFG_PCIE2_MEM_BASE,
 331                                CFG_PCIE2_MEM_PHYS,
 332                                CFG_PCIE2_MEM_SIZE,
 333                                PCI_REGION_MEM);
 334
 335                 /* outbound io */
 336                 pci_set_region(hose->regions + 2,
 337                                CFG_PCIE2_IO_BASE,
 338                                CFG_PCIE2_IO_PHYS,
 339                                CFG_PCIE2_IO_SIZE,
 340                                PCI_REGION_IO);
 341
 342                 hose->region_count = 3;
 343 #ifdef CFG_PCIE2_MEM_BASE2
 344                 /* outbound memory */
 345                 pci_set_region(hose->regions + 3,
 346                                CFG_PCIE2_MEM_BASE2,
 347                                CFG_PCIE2_MEM_PHYS2,
 348                                CFG_PCIE2_MEM_SIZE2,
 349                                PCI_REGION_MEM);
 350                 hose->region_count++;
 351 #endif
 352                 hose->first_busno=first_free_busno;
 353                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 354
 355                 fsl_pci_init(hose);
 356                 first_free_busno=hose->last_busno+1;
 357                 printf ("    PCIE2 on bus %02x - %02x\n",
 358                         hose->first_busno,hose->last_busno);
 359
 360         } else {
 361                 printf ("    PCIE2: disabled\n");
 362         }
 363
 364  }
 365 #else
 366         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 367 #endif
 368
 369
 370 #ifdef CONFIG_PCI1
 371 {
 372         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 373         extern void fsl_pci_init(struct pci_controller *hose);
 374         struct pci_controller *hose = &pci1_hose;
 375
 376         uint pci_agent = (host_agent == 6);
 377         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 378         uint pci_32 = 1;
 379         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 380         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 381
 382
 383         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 384                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 385                         (pci_32) ? 32 : 64,
 386                         (pci_speed == 33333000) ? "33" :
 387                         (pci_speed == 66666000) ? "66" : "unknown",
 388                         pci_clk_sel ? "sync" : "async",
 389                         pci_agent ? "agent" : "host",
 390                         pci_arb ? "arbiter" : "external-arbiter",
 391                         (uint)pci
 392                         );
 393
 394                 /* inbound */
 395                 pci_set_region(hose->regions + 0,
 396                                CFG_PCI_MEMORY_BUS,
 397                                CFG_PCI_MEMORY_PHYS,
 398                                CFG_PCI_MEMORY_SIZE,
 399                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 400
 401                 /* outbound memory */
 402                 pci_set_region(hose->regions + 1,
 403                                CFG_PCI1_MEM_BASE,
 404                                CFG_PCI1_MEM_PHYS,
 405                                CFG_PCI1_MEM_SIZE,
 406                                PCI_REGION_MEM);
 407
 408                 /* outbound io */
 409                 pci_set_region(hose->regions + 2,
 410                                CFG_PCI1_IO_BASE,
 411                                CFG_PCI1_IO_PHYS,
 412                                CFG_PCI1_IO_SIZE,
 413                                PCI_REGION_IO);
 414                 hose->region_count = 3;
 415 #ifdef CFG_PCIE3_MEM_BASE2
 416                 /* outbound memory */
 417                 pci_set_region(hose->regions + 3,
 418                                CFG_PCIE3_MEM_BASE2,
 419                                CFG_PCIE3_MEM_PHYS2,
 420                                CFG_PCIE3_MEM_SIZE2,
 421                                PCI_REGION_MEM);
 422                 hose->region_count++;
 423 #endif
 424                 hose->first_busno=first_free_busno;
 425                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 426
 427                 fsl_pci_init(hose);
 428                 first_free_busno=hose->last_busno+1;
 429                 printf ("PCI on bus %02x - %02x\n",
 430                         hose->first_busno,hose->last_busno);
 431         } else {
 432                 printf ("    PCI: disabled\n");
 433         }
 434 }
 435 #else
 436         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 437 #endif
 438 }
 439
 440
 441 int last_stage_init(void)
 442 {
 443         return 0;
 444 }
 445
 446
 447 unsigned long
 448 get_board_sys_clk(ulong dummy)
 449 {
 450         u8 i, go_bit, rd_clks;
 451         ulong val = 0;
 452
 453         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 454         go_bit &= 0x01;
 455
 456         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 457         rd_clks &= 0x1C;
 458
 459         /*
 460          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 461          * should we be using the AUX register. Remember, we also set the
 462          * GO bit to boot from the alternate bank on the on-board flash
 463          */
 464
 465         if (go_bit) {
 466                 if (rd_clks == 0x1c)
 467                         i = in8(PIXIS_BASE + PIXIS_AUX);
 468                 else
 469                         i = in8(PIXIS_BASE + PIXIS_SPD);
 470         } else {
 471                 i = in8(PIXIS_BASE + PIXIS_SPD);
 472         }
 473
 474         i &= 0x07;
 475
 476         switch (i) {
 477         case 0:
 478                 val = 33333333;
 479                 break;
 480         case 1:
 481                 val = 40000000;
 482                 break;
 483         case 2:
 484                 val = 50000000;
 485                 break;
 486         case 3:
 487                 val = 66666666;
 488                 break;
 489         case 4:
 490                 val = 83000000;
 491                 break;
 492         case 5:
 493                 val = 100000000;
 494                 break;
 495         case 6:
 496                 val = 133333333;
 497                 break;
 498         case 7:
 499                 val = 166666666;
 500                 break;
 501         }
 502
 503         return val;
 504 }
 505
 506 #if defined(CONFIG_OF_BOARD_SETUP)
 507
 508 void
 509 ft_board_setup(void *blob, bd_t *bd)
 510 {
 511         int node, tmp[2];
 512         const char *path;
 513
 514         ft_cpu_setup(blob, bd);
 515
 516         node = fdt_path_offset(blob, "/aliases");
 517         tmp[0] = 0;
 518         if (node >= 0) {
 519 #ifdef CONFIG_PCI1
 520                 path = fdt_getprop(blob, node, "pci0", NULL);
 521                 if (path) {
 522                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 523                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 524                 }
 525 #endif
 526 #ifdef CONFIG_PCIE2
 527                 path = fdt_getprop(blob, node, "pci1", NULL);
 528                 if (path) {
 529                         tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 530                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 531                 }
 532 #endif
 533 #ifdef CONFIG_PCIE1
 534                 path = fdt_getprop(blob, node, "pci2", NULL);
 535                 if (path) {
 536                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 537                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 538                 }
 539 #endif
 540 #ifdef CONFIG_PCIE3
 541                 path = fdt_getprop(blob, node, "pci3", NULL);
 542                 if (path) {
 543                         tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
 544                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 545                 }
 546 #endif
 547         }
 548 }
 549 #endif