board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_85xx.h>
  28 #include <asm/immap_fsl_pci.h>
  29 #include <asm/io.h>
  30 #include <spd.h>
  31 #include <miiphy.h>
  32 #include <libfdt.h>
  33 #include <fdt_support.h>
  34
  35 #include "../common/pixis.h"
  36
  37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  38 extern void ddr_enable_ecc(unsigned int dram_size);
  39 #endif
  40
  41 extern long int spd_sdram(void);
  42
  43 void sdram_init(void);
  44
  45 int board_early_init_f (void)
  46 {
  47         return 0;
  48 }
  49
  50 int checkboard (void)
  51 {
  52         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
  53         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  54         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  55         volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
  56
  57         if ((uint)&gur->porpllsr != 0xe00e0000) {
  58                 printf("immap size error %x\n",&gur->porpllsr);
  59         }
  60         printf ("Board: MPC8544DS\n");
  61
  62         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  63         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  64         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  65         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  66
  67         return 0;
  68 }
  69
  70 long int
  71 initdram(int board_type)
  72 {
  73         long dram_size = 0;
  74
  75         puts("Initializing\n");
  76
  77         dram_size = spd_sdram();
  78
  79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  80         /*
  81          * Initialize and enable DDR ECC.
  82          */
  83         ddr_enable_ecc(dram_size);
  84 #endif
  85         puts("    DDR: ");
  86         return dram_size;
  87 }
  88
  89 #if defined(CFG_DRAM_TEST)
  90 int
  91 testdram(void)
  92 {
  93         uint *pstart = (uint *) CFG_MEMTEST_START;
  94         uint *pend = (uint *) CFG_MEMTEST_END;
  95         uint *p;
  96
  97         printf("Testing DRAM from 0x%08x to 0x%08x\n",
  98                CFG_MEMTEST_START,
  99                CFG_MEMTEST_END);
 100
 101         printf("DRAM test phase 1:\n");
 102         for (p = pstart; p < pend; p++)
 103                 *p = 0xaaaaaaaa;
 104
 105         for (p = pstart; p < pend; p++) {
 106                 if (*p != 0xaaaaaaaa) {
 107                         printf ("DRAM test fails at: %08x\n", (uint) p);
 108                         return 1;
 109                 }
 110         }
 111
 112         printf("DRAM test phase 2:\n");
 113         for (p = pstart; p < pend; p++)
 114                 *p = 0x55555555;
 115
 116         for (p = pstart; p < pend; p++) {
 117                 if (*p != 0x55555555) {
 118                         printf ("DRAM test fails at: %08x\n", (uint) p);
 119                         return 1;
 120                 }
 121         }
 122
 123         printf("DRAM test passed.\n");
 124         return 0;
 125 }
 126 #endif
 127
 128 #ifdef CONFIG_PCI1
 129 static struct pci_controller pci1_hose;
 130 #endif
 131
 132 #ifdef CONFIG_PCIE1
 133 static struct pci_controller pcie1_hose;
 134 #endif
 135
 136 #ifdef CONFIG_PCIE2
 137 static struct pci_controller pcie2_hose;
 138 #endif
 139
 140 #ifdef CONFIG_PCIE3
 141 static struct pci_controller pcie3_hose;
 142 #endif
 143
 144 int first_free_busno=0;
 145
 146 void
 147 pci_init_board(void)
 148 {
 149         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 150         uint devdisr = gur->devdisr;
 151         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 152         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 153
 154         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 155                 devdisr, io_sel, host_agent);
 156
 157         if (io_sel & 1) {
 158                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 159                         printf ("    eTSEC1 is in sgmii mode.\n");
 160                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 161                         printf ("    eTSEC3 is in sgmii mode.\n");
 162         }
 163
 164 #ifdef CONFIG_PCIE3
 165 {
 166         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
 167         extern void fsl_pci_init(struct pci_controller *hose);
 168         struct pci_controller *hose = &pcie3_hose;
 169         int pcie_ep = (host_agent == 3);
 170         int pcie_configured  = io_sel >= 1;
 171
 172         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 173                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 174                         pcie_ep ? "End Point" : "Root Complex",
 175                         (uint)pci);
 176                 if (pci->pme_msg_det) {
 177                         pci->pme_msg_det = 0xffffffff;
 178                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 179                 }
 180                 printf ("\n");
 181
 182                 /* inbound */
 183                 pci_set_region(hose->regions + 0,
 184                                CFG_PCI_MEMORY_BUS,
 185                                CFG_PCI_MEMORY_PHYS,
 186                                CFG_PCI_MEMORY_SIZE,
 187                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 188
 189                 /* outbound memory */
 190                 pci_set_region(hose->regions + 1,
 191                                CFG_PCIE3_MEM_BASE,
 192                                CFG_PCIE3_MEM_PHYS,
 193                                CFG_PCIE3_MEM_SIZE,
 194                                PCI_REGION_MEM);
 195
 196                 /* outbound io */
 197                 pci_set_region(hose->regions + 2,
 198                                CFG_PCIE3_IO_BASE,
 199                                CFG_PCIE3_IO_PHYS,
 200                                CFG_PCIE3_IO_SIZE,
 201                                PCI_REGION_IO);
 202
 203                 hose->region_count = 3;
 204 #ifdef CFG_PCIE3_MEM_BASE2
 205                 /* outbound memory */
 206                 pci_set_region(hose->regions + 3,
 207                                CFG_PCIE3_MEM_BASE2,
 208                                CFG_PCIE3_MEM_PHYS2,
 209                                CFG_PCIE3_MEM_SIZE2,
 210                                PCI_REGION_MEM);
 211                 hose->region_count++;
 212 #endif
 213                 hose->first_busno=first_free_busno;
 214                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 215
 216                 fsl_pci_init(hose);
 217
 218                 first_free_busno=hose->last_busno+1;
 219                 printf ("    PCIE3 on bus %02x - %02x\n",
 220                         hose->first_busno,hose->last_busno);
 221
 222                 /*
 223                  * Activate ULI1575 legacy chip by performing a fake
 224                  * memory access.  Needed to make ULI RTC work.
 225                  */
 226                 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
 227         } else {
 228                 printf ("    PCIE3: disabled\n");
 229         }
 230
 231  }
 232 #else
 233         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 234 #endif
 235
 236 #ifdef CONFIG_PCIE1
 237  {
 238         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 239         extern void fsl_pci_init(struct pci_controller *hose);
 240         struct pci_controller *hose = &pcie1_hose;
 241         int pcie_ep = (host_agent == 5);
 242         int pcie_configured  = io_sel & 6;
 243
 244         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 245                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 246                         pcie_ep ? "End Point" : "Root Complex",
 247                         (uint)pci);
 248                 if (pci->pme_msg_det) {
 249                         pci->pme_msg_det = 0xffffffff;
 250                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 251                 }
 252                 printf ("\n");
 253
 254                 /* inbound */
 255                 pci_set_region(hose->regions + 0,
 256                                CFG_PCI_MEMORY_BUS,
 257                                CFG_PCI_MEMORY_PHYS,
 258                                CFG_PCI_MEMORY_SIZE,
 259                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 260
 261                 /* outbound memory */
 262                 pci_set_region(hose->regions + 1,
 263                                CFG_PCIE1_MEM_BASE,
 264                                CFG_PCIE1_MEM_PHYS,
 265                                CFG_PCIE1_MEM_SIZE,
 266                                PCI_REGION_MEM);
 267
 268                 /* outbound io */
 269                 pci_set_region(hose->regions + 2,
 270                                CFG_PCIE1_IO_BASE,
 271                                CFG_PCIE1_IO_PHYS,
 272                                CFG_PCIE1_IO_SIZE,
 273                                PCI_REGION_IO);
 274
 275                 hose->region_count = 3;
 276 #ifdef CFG_PCIE1_MEM_BASE2
 277                 /* outbound memory */
 278                 pci_set_region(hose->regions + 3,
 279                                CFG_PCIE1_MEM_BASE2,
 280                                CFG_PCIE1_MEM_PHYS2,
 281                                CFG_PCIE1_MEM_SIZE2,
 282                                PCI_REGION_MEM);
 283                 hose->region_count++;
 284 #endif
 285                 hose->first_busno=first_free_busno;
 286
 287                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 288
 289                 fsl_pci_init(hose);
 290
 291                 first_free_busno=hose->last_busno+1;
 292                 printf("    PCIE1 on bus %02x - %02x\n",
 293                        hose->first_busno,hose->last_busno);
 294
 295         } else {
 296                 printf ("    PCIE1: disabled\n");
 297         }
 298
 299  }
 300 #else
 301         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 302 #endif
 303
 304 #ifdef CONFIG_PCIE2
 305  {
 306         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 307         extern void fsl_pci_init(struct pci_controller *hose);
 308         struct pci_controller *hose = &pcie2_hose;
 309         int pcie_ep = (host_agent == 3);
 310         int pcie_configured  = io_sel & 4;
 311
 312         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 313                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 314                         pcie_ep ? "End Point" : "Root Complex",
 315                         (uint)pci);
 316                 if (pci->pme_msg_det) {
 317                         pci->pme_msg_det = 0xffffffff;
 318                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 319                 }
 320                 printf ("\n");
 321
 322                 /* inbound */
 323                 pci_set_region(hose->regions + 0,
 324                                CFG_PCI_MEMORY_BUS,
 325                                CFG_PCI_MEMORY_PHYS,
 326                                CFG_PCI_MEMORY_SIZE,
 327                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 328
 329                 /* outbound memory */
 330                 pci_set_region(hose->regions + 1,
 331                                CFG_PCIE2_MEM_BASE,
 332                                CFG_PCIE2_MEM_PHYS,
 333                                CFG_PCIE2_MEM_SIZE,
 334                                PCI_REGION_MEM);
 335
 336                 /* outbound io */
 337                 pci_set_region(hose->regions + 2,
 338                                CFG_PCIE2_IO_BASE,
 339                                CFG_PCIE2_IO_PHYS,
 340                                CFG_PCIE2_IO_SIZE,
 341                                PCI_REGION_IO);
 342
 343                 hose->region_count = 3;
 344 #ifdef CFG_PCIE2_MEM_BASE2
 345                 /* outbound memory */
 346                 pci_set_region(hose->regions + 3,
 347                                CFG_PCIE2_MEM_BASE2,
 348                                CFG_PCIE2_MEM_PHYS2,
 349                                CFG_PCIE2_MEM_SIZE2,
 350                                PCI_REGION_MEM);
 351                 hose->region_count++;
 352 #endif
 353                 hose->first_busno=first_free_busno;
 354                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 355
 356                 fsl_pci_init(hose);
 357                 first_free_busno=hose->last_busno+1;
 358                 printf ("    PCIE2 on bus %02x - %02x\n",
 359                         hose->first_busno,hose->last_busno);
 360
 361         } else {
 362                 printf ("    PCIE2: disabled\n");
 363         }
 364
 365  }
 366 #else
 367         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 368 #endif
 369
 370
 371 #ifdef CONFIG_PCI1
 372 {
 373         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 374         extern void fsl_pci_init(struct pci_controller *hose);
 375         struct pci_controller *hose = &pci1_hose;
 376
 377         uint pci_agent = (host_agent == 6);
 378         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 379         uint pci_32 = 1;
 380         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 381         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 382
 383
 384         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 385                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 386                         (pci_32) ? 32 : 64,
 387                         (pci_speed == 33333000) ? "33" :
 388                         (pci_speed == 66666000) ? "66" : "unknown",
 389                         pci_clk_sel ? "sync" : "async",
 390                         pci_agent ? "agent" : "host",
 391                         pci_arb ? "arbiter" : "external-arbiter",
 392                         (uint)pci
 393                         );
 394
 395                 /* inbound */
 396                 pci_set_region(hose->regions + 0,
 397                                CFG_PCI_MEMORY_BUS,
 398                                CFG_PCI_MEMORY_PHYS,
 399                                CFG_PCI_MEMORY_SIZE,
 400                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 401
 402                 /* outbound memory */
 403                 pci_set_region(hose->regions + 1,
 404                                CFG_PCI1_MEM_BASE,
 405                                CFG_PCI1_MEM_PHYS,
 406                                CFG_PCI1_MEM_SIZE,
 407                                PCI_REGION_MEM);
 408
 409                 /* outbound io */
 410                 pci_set_region(hose->regions + 2,
 411                                CFG_PCI1_IO_BASE,
 412                                CFG_PCI1_IO_PHYS,
 413                                CFG_PCI1_IO_SIZE,
 414                                PCI_REGION_IO);
 415                 hose->region_count = 3;
 416 #ifdef CFG_PCIE3_MEM_BASE2
 417                 /* outbound memory */
 418                 pci_set_region(hose->regions + 3,
 419                                CFG_PCIE3_MEM_BASE2,
 420                                CFG_PCIE3_MEM_PHYS2,
 421                                CFG_PCIE3_MEM_SIZE2,
 422                                PCI_REGION_MEM);
 423                 hose->region_count++;
 424 #endif
 425                 hose->first_busno=first_free_busno;
 426                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 427
 428                 fsl_pci_init(hose);
 429                 first_free_busno=hose->last_busno+1;
 430                 printf ("PCI on bus %02x - %02x\n",
 431                         hose->first_busno,hose->last_busno);
 432         } else {
 433                 printf ("    PCI: disabled\n");
 434         }
 435 }
 436 #else
 437         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 438 #endif
 439 }
 440
 441
 442 int last_stage_init(void)
 443 {
 444         return 0;
 445 }
 446
 447
 448 unsigned long
 449 get_board_sys_clk(ulong dummy)
 450 {
 451         u8 i, go_bit, rd_clks;
 452         ulong val = 0;
 453
 454         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 455         go_bit &= 0x01;
 456
 457         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 458         rd_clks &= 0x1C;
 459
 460         /*
 461          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 462          * should we be using the AUX register. Remember, we also set the
 463          * GO bit to boot from the alternate bank on the on-board flash
 464          */
 465
 466         if (go_bit) {
 467                 if (rd_clks == 0x1c)
 468                         i = in8(PIXIS_BASE + PIXIS_AUX);
 469                 else
 470                         i = in8(PIXIS_BASE + PIXIS_SPD);
 471         } else {
 472                 i = in8(PIXIS_BASE + PIXIS_SPD);
 473         }
 474
 475         i &= 0x07;
 476
 477         switch (i) {
 478         case 0:
 479                 val = 33333333;
 480                 break;
 481         case 1:
 482                 val = 40000000;
 483                 break;
 484         case 2:
 485                 val = 50000000;
 486                 break;
 487         case 3:
 488                 val = 66666666;
 489                 break;
 490         case 4:
 491                 val = 83000000;
 492                 break;
 493         case 5:
 494                 val = 100000000;
 495                 break;
 496         case 6:
 497                 val = 133333333;
 498                 break;
 499         case 7:
 500                 val = 166666666;
 501                 break;
 502         }
 503
 504         return val;
 505 }
 506
 507 #if defined(CONFIG_OF_BOARD_SETUP)
 508
 509 void
 510 ft_board_setup(void *blob, bd_t *bd)
 511 {
 512         int node, tmp[2];
 513         const char *path;
 514
 515         ft_cpu_setup(blob, bd);
 516
 517         node = fdt_path_offset(blob, "/aliases");
 518         tmp[0] = 0;
 519         if (node >= 0) {
 520 #ifdef CONFIG_PCI1
 521                 path = fdt_getprop(blob, node, "pci0", NULL);
 522                 if (path) {
 523                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 524                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 525                 }
 526 #endif
 527 #ifdef CONFIG_PCIE2
 528                 path = fdt_getprop(blob, node, "pci1", NULL);
 529                 if (path) {
 530                         tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 531                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 532                 }
 533 #endif
 534 #ifdef CONFIG_PCIE1
 535                 path = fdt_getprop(blob, node, "pci2", NULL);
 536                 if (path) {
 537                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 538                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 539                 }
 540 #endif
 541 #ifdef CONFIG_PCIE3
 542                 path = fdt_getprop(blob, node, "pci3", NULL);
 543                 if (path) {
 544                         tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
 545                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 546                 }
 547 #endif
 548         }
 549 }
 550 #endif