board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_85xx.h>
  28 #include <asm/immap_fsl_pci.h>
  29 #include <spd.h>
  30 #include <miiphy.h>
  31
  32 #include "../common/pixis.h"
  33
  34 #if defined(CONFIG_OF_FLAT_TREE)
  35 #include <ft_build.h>
  36 extern void ft_cpu_setup(void *blob, bd_t *bd);
  37 #endif
  38
  39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  40 extern void ddr_enable_ecc(unsigned int dram_size);
  41 #endif
  42
  43 extern long int spd_sdram(void);
  44
  45 void sdram_init(void);
  46
  47 int board_early_init_f (void)
  48 {
  49         return 0;
  50 }
  51
  52 int checkboard (void)
  53 {
  54         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
  55         volatile ccsr_gur_t *gur = &immap->im_gur;
  56         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  57         volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
  58
  59         if ((uint)&gur->porpllsr != 0xe00e0000) {
  60                 printf("immap size error %x\n",&gur->porpllsr);
  61         }
  62         printf ("Board: MPC8544DS\n");
  63
  64         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  65         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  66         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  67         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  68
  69         return 0;
  70 }
  71
  72 long int
  73 initdram(int board_type)
  74 {
  75         long dram_size = 0;
  76
  77         puts("Initializing\n");
  78
  79         dram_size = spd_sdram();
  80
  81 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  82         /*
  83          * Initialize and enable DDR ECC.
  84          */
  85         ddr_enable_ecc(dram_size);
  86 #endif
  87         puts("    DDR: ");
  88         return dram_size;
  89 }
  90
  91 #if defined(CFG_DRAM_TEST)
  92 int
  93 testdram(void)
  94 {
  95         uint *pstart = (uint *) CFG_MEMTEST_START;
  96         uint *pend = (uint *) CFG_MEMTEST_END;
  97         uint *p;
  98
  99         printf("Testing DRAM from 0x%08x to 0x%08x\n",
 100                CFG_MEMTEST_START,
 101                CFG_MEMTEST_END);
 102
 103         printf("DRAM test phase 1:\n");
 104         for (p = pstart; p < pend; p++)
 105                 *p = 0xaaaaaaaa;
 106
 107         for (p = pstart; p < pend; p++) {
 108                 if (*p != 0xaaaaaaaa) {
 109                         printf ("DRAM test fails at: %08x\n", (uint) p);
 110                         return 1;
 111                 }
 112         }
 113
 114         printf("DRAM test phase 2:\n");
 115         for (p = pstart; p < pend; p++)
 116                 *p = 0x55555555;
 117
 118         for (p = pstart; p < pend; p++) {
 119                 if (*p != 0x55555555) {
 120                         printf ("DRAM test fails at: %08x\n", (uint) p);
 121                         return 1;
 122                 }
 123         }
 124
 125         printf("DRAM test passed.\n");
 126         return 0;
 127 }
 128 #endif
 129
 130 #ifdef CONFIG_PCI1
 131 static struct pci_controller pci1_hose;
 132 #endif
 133
 134 #ifdef CONFIG_PCIE1
 135 static struct pci_controller pcie1_hose;
 136 #endif
 137
 138 #ifdef CONFIG_PCIE2
 139 static struct pci_controller pcie2_hose;
 140 #endif
 141
 142 #ifdef CONFIG_PCIE3
 143 static struct pci_controller pcie3_hose;
 144 #endif
 145
 146 int first_free_busno=0;
 147
 148 void
 149 pci_init_board(void)
 150 {
 151         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 152         volatile ccsr_gur_t *gur = &immap->im_gur;
 153         uint devdisr = gur->devdisr;
 154         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 155         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 156
 157         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 158                 devdisr, io_sel, host_agent);
 159
 160         if (io_sel & 1) {
 161                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 162                         printf ("    eTSEC1 is in sgmii mode.\n");
 163                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 164                         printf ("    eTSEC3 is in sgmii mode.\n");
 165         }
 166
 167 #ifdef CONFIG_PCIE3
 168 {
 169         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
 170         extern void fsl_pci_init(struct pci_controller *hose);
 171         struct pci_controller *hose = &pcie3_hose;
 172         int pcie_ep = (host_agent == 3);
 173         int pcie_configured  = io_sel >= 1;
 174
 175         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 176                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 177                         pcie_ep ? "End Point" : "Root Complex",
 178                         (uint)pci);
 179                 if (pci->pme_msg_det) {
 180                         pci->pme_msg_det = 0xffffffff;
 181                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 182                 }
 183                 printf ("\n");
 184
 185                 /* inbound */
 186                 pci_set_region(hose->regions + 0,
 187                                CFG_PCI_MEMORY_BUS,
 188                                CFG_PCI_MEMORY_PHYS,
 189                                CFG_PCI_MEMORY_SIZE,
 190                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 191
 192                 /* outbound memory */
 193                 pci_set_region(hose->regions + 1,
 194                                CFG_PCIE3_MEM_BASE,
 195                                CFG_PCIE3_MEM_PHYS,
 196                                CFG_PCIE3_MEM_SIZE,
 197                                PCI_REGION_MEM);
 198
 199                 /* outbound io */
 200                 pci_set_region(hose->regions + 2,
 201                                CFG_PCIE3_IO_BASE,
 202                                CFG_PCIE3_IO_PHYS,
 203                                CFG_PCIE3_IO_SIZE,
 204                                PCI_REGION_IO);
 205
 206                 hose->region_count = 3;
 207 #ifdef CFG_PCIE3_MEM_BASE2
 208                 /* outbound memory */
 209                 pci_set_region(hose->regions + 3,
 210                                CFG_PCIE3_MEM_BASE2,
 211                                CFG_PCIE3_MEM_PHYS2,
 212                                CFG_PCIE3_MEM_SIZE2,
 213                                PCI_REGION_MEM);
 214                 hose->region_count++;
 215 #endif
 216                 hose->first_busno=first_free_busno;
 217                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 218
 219                 fsl_pci_init(hose);
 220
 221                 first_free_busno=hose->last_busno+1;
 222                 printf ("    PCIE3 on bus %02x - %02x\n",
 223                         hose->first_busno,hose->last_busno);
 224
 225         } else {
 226                 printf ("    PCIE3: disabled\n");
 227         }
 228
 229  }
 230 #else
 231         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 232 #endif
 233
 234 #ifdef CONFIG_PCIE1
 235  {
 236         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 237         extern void fsl_pci_init(struct pci_controller *hose);
 238         struct pci_controller *hose = &pcie1_hose;
 239         int pcie_ep = (host_agent == 5);
 240         int pcie_configured  = io_sel & 6;
 241
 242         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 243                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 244                         pcie_ep ? "End Point" : "Root Complex",
 245                         (uint)pci);
 246                 if (pci->pme_msg_det) {
 247                         pci->pme_msg_det = 0xffffffff;
 248                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 249                 }
 250                 printf ("\n");
 251
 252                 /* inbound */
 253                 pci_set_region(hose->regions + 0,
 254                                CFG_PCI_MEMORY_BUS,
 255                                CFG_PCI_MEMORY_PHYS,
 256                                CFG_PCI_MEMORY_SIZE,
 257                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 258
 259                 /* outbound memory */
 260                 pci_set_region(hose->regions + 1,
 261                                CFG_PCIE1_MEM_BASE,
 262                                CFG_PCIE1_MEM_PHYS,
 263                                CFG_PCIE1_MEM_SIZE,
 264                                PCI_REGION_MEM);
 265
 266                 /* outbound io */
 267                 pci_set_region(hose->regions + 2,
 268                                CFG_PCIE1_IO_BASE,
 269                                CFG_PCIE1_IO_PHYS,
 270                                CFG_PCIE1_IO_SIZE,
 271                                PCI_REGION_IO);
 272
 273                 hose->region_count = 3;
 274 #ifdef CFG_PCIE1_MEM_BASE2
 275                 /* outbound memory */
 276                 pci_set_region(hose->regions + 3,
 277                                CFG_PCIE1_MEM_BASE2,
 278                                CFG_PCIE1_MEM_PHYS2,
 279                                CFG_PCIE1_MEM_SIZE2,
 280                                PCI_REGION_MEM);
 281                 hose->region_count++;
 282 #endif
 283                 hose->first_busno=first_free_busno;
 284
 285                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 286
 287                 fsl_pci_init(hose);
 288
 289                 first_free_busno=hose->last_busno+1;
 290                 printf("    PCIE1 on bus %02x - %02x\n",
 291                        hose->first_busno,hose->last_busno);
 292
 293         } else {
 294                 printf ("    PCIE1: disabled\n");
 295         }
 296
 297  }
 298 #else
 299         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 300 #endif
 301
 302 #ifdef CONFIG_PCIE2
 303  {
 304         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 305         extern void fsl_pci_init(struct pci_controller *hose);
 306         struct pci_controller *hose = &pcie2_hose;
 307         int pcie_ep = (host_agent == 3);
 308         int pcie_configured  = io_sel & 4;
 309
 310         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 311                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 312                         pcie_ep ? "End Point" : "Root Complex",
 313                         (uint)pci);
 314                 if (pci->pme_msg_det) {
 315                         pci->pme_msg_det = 0xffffffff;
 316                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 317                 }
 318                 printf ("\n");
 319
 320                 /* inbound */
 321                 pci_set_region(hose->regions + 0,
 322                                CFG_PCI_MEMORY_BUS,
 323                                CFG_PCI_MEMORY_PHYS,
 324                                CFG_PCI_MEMORY_SIZE,
 325                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 326
 327                 /* outbound memory */
 328                 pci_set_region(hose->regions + 1,
 329                                CFG_PCIE2_MEM_BASE,
 330                                CFG_PCIE2_MEM_PHYS,
 331                                CFG_PCIE2_MEM_SIZE,
 332                                PCI_REGION_MEM);
 333
 334                 /* outbound io */
 335                 pci_set_region(hose->regions + 2,
 336                                CFG_PCIE2_IO_BASE,
 337                                CFG_PCIE2_IO_PHYS,
 338                                CFG_PCIE2_IO_SIZE,
 339                                PCI_REGION_IO);
 340
 341                 hose->region_count = 3;
 342 #ifdef CFG_PCIE2_MEM_BASE2
 343                 /* outbound memory */
 344                 pci_set_region(hose->regions + 3,
 345                                CFG_PCIE2_MEM_BASE2,
 346                                CFG_PCIE2_MEM_PHYS2,
 347                                CFG_PCIE2_MEM_SIZE2,
 348                                PCI_REGION_MEM);
 349                 hose->region_count++;
 350 #endif
 351                 hose->first_busno=first_free_busno;
 352                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 353
 354                 fsl_pci_init(hose);
 355                 first_free_busno=hose->last_busno+1;
 356                 printf ("    PCIE2 on bus %02x - %02x\n",
 357                         hose->first_busno,hose->last_busno);
 358
 359         } else {
 360                 printf ("    PCIE2: disabled\n");
 361         }
 362
 363  }
 364 #else
 365         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 366 #endif
 367
 368
 369 #ifdef CONFIG_PCI1
 370 {
 371         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 372         extern void fsl_pci_init(struct pci_controller *hose);
 373         struct pci_controller *hose = &pci1_hose;
 374
 375         uint pci_agent = (host_agent == 6);
 376         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 377         uint pci_32 = 1;
 378         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 379         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 380
 381
 382         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 383                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 384                         (pci_32) ? 32 : 64,
 385                         (pci_speed == 33333000) ? "33" :
 386                         (pci_speed == 66666000) ? "66" : "unknown",
 387                         pci_clk_sel ? "sync" : "async",
 388                         pci_agent ? "agent" : "host",
 389                         pci_arb ? "arbiter" : "external-arbiter",
 390                         (uint)pci
 391                         );
 392
 393                 /* inbound */
 394                 pci_set_region(hose->regions + 0,
 395                                CFG_PCI_MEMORY_BUS,
 396                                CFG_PCI_MEMORY_PHYS,
 397                                CFG_PCI_MEMORY_SIZE,
 398                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 399
 400                 /* outbound memory */
 401                 pci_set_region(hose->regions + 1,
 402                                CFG_PCI1_MEM_BASE,
 403                                CFG_PCI1_MEM_PHYS,
 404                                CFG_PCI1_MEM_SIZE,
 405                                PCI_REGION_MEM);
 406
 407                 /* outbound io */
 408                 pci_set_region(hose->regions + 2,
 409                                CFG_PCI1_IO_BASE,
 410                                CFG_PCI1_IO_PHYS,
 411                                CFG_PCI1_IO_SIZE,
 412                                PCI_REGION_IO);
 413                 hose->region_count = 3;
 414 #ifdef CFG_PCIE3_MEM_BASE2
 415                 /* outbound memory */
 416                 pci_set_region(hose->regions + 3,
 417                                CFG_PCIE3_MEM_BASE2,
 418                                CFG_PCIE3_MEM_PHYS2,
 419                                CFG_PCIE3_MEM_SIZE2,
 420                                PCI_REGION_MEM);
 421                 hose->region_count++;
 422 #endif
 423                 hose->first_busno=first_free_busno;
 424                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 425
 426                 fsl_pci_init(hose);
 427                 first_free_busno=hose->last_busno+1;
 428                 printf ("PCI on bus %02x - %02x\n",
 429                         hose->first_busno,hose->last_busno);
 430         } else {
 431                 printf ("    PCI: disabled\n");
 432         }
 433 }
 434 #else
 435         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 436 #endif
 437 }
 438
 439
 440 int last_stage_init(void)
 441 {
 442         return 0;
 443 }
 444
 445
 446 unsigned long
 447 get_board_sys_clk(ulong dummy)
 448 {
 449         u8 i, go_bit, rd_clks;
 450         ulong val = 0;
 451
 452         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 453         go_bit &= 0x01;
 454
 455         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 456         rd_clks &= 0x1C;
 457
 458         /*
 459          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 460          * should we be using the AUX register. Remember, we also set the
 461          * GO bit to boot from the alternate bank on the on-board flash
 462          */
 463
 464         if (go_bit) {
 465                 if (rd_clks == 0x1c)
 466                         i = in8(PIXIS_BASE + PIXIS_AUX);
 467                 else
 468                         i = in8(PIXIS_BASE + PIXIS_SPD);
 469         } else {
 470                 i = in8(PIXIS_BASE + PIXIS_SPD);
 471         }
 472
 473         i &= 0x07;
 474
 475         switch (i) {
 476         case 0:
 477                 val = 33333333;
 478                 break;
 479         case 1:
 480                 val = 40000000;
 481                 break;
 482         case 2:
 483                 val = 50000000;
 484                 break;
 485         case 3:
 486                 val = 66666666;
 487                 break;
 488         case 4:
 489                 val = 83000000;
 490                 break;
 491         case 5:
 492                 val = 100000000;
 493                 break;
 494         case 6:
 495                 val = 133333333;
 496                 break;
 497         case 7:
 498                 val = 166666666;
 499                 break;
 500         }
 501
 502         return val;
 503 }
 504
 505 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 506 void
 507 ft_board_setup(void *blob, bd_t *bd)
 508 {
 509         u32 *p;
 510         int len;
 511
 512         ft_cpu_setup(blob, bd);
 513
 514         p = ft_get_prop(blob, "/memory/reg", &len);
 515         if (p != NULL) {
 516                 *p++ = cpu_to_be32(bd->bi_memstart);
 517                 *p = cpu_to_be32(bd->bi_memsize);
 518         }
 519 #ifdef CONFIG_PCI1
 520         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
 521         if (p != NULL) {
 522                 p[0] = 0;
 523                 p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 524                 debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 525         }
 526 #endif
 527 #ifdef CONFIG_PCIE1
 528         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
 529         if (p != NULL) {
 530                 p[0] = 0;
 531                 p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 532                 debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 533         }
 534 #endif
 535 #ifdef CONFIG_PCIE2
 536         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
 537         if (p != NULL) {
 538                 p[0] = 0;
 539                 p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 540                 debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 541         }
 542 #endif
 543 #ifdef CONFIG_PCIE3
 544         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
 545         if (p != NULL) {
 546                 p[0] = 0;
 547                 p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
 548                 debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 549         }
 550 #endif
 551 }
 552 #endif