2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/immap_fsl_pci.h>
30 #include <spd_sdram.h>
33 #include <fdt_support.h>
35 #include "../common/pixis.h"
37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38 extern void ddr_enable_ecc(unsigned int dram_size
);
41 void sdram_init(void);
43 int board_early_init_f (void)
50 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
51 volatile ccsr_lbc_t
*lbc
= (void *)(CFG_MPC85xx_LBC_ADDR
);
52 volatile ccsr_local_ecm_t
*ecm
= (void *)(CFG_MPC85xx_ECM_ADDR
);
54 if ((uint
)&gur
->porpllsr
!= 0xe00e0000) {
55 printf("immap size error %x\n",&gur
->porpllsr
);
57 printf ("Board: MPC8544DS\n");
59 lbc
->ltesr
= 0xffffffff; /* Clear LBC error interrupts */
60 lbc
->lteir
= 0xffffffff; /* Enable LBC error interrupts */
61 ecm
->eedr
= 0xffffffff; /* Clear ecm errors */
62 ecm
->eeer
= 0xffffffff; /* Enable ecm errors */
68 initdram(int board_type
)
72 puts("Initializing\n");
74 dram_size
= spd_sdram();
76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
78 * Initialize and enable DDR ECC.
80 ddr_enable_ecc(dram_size
);
86 #if defined(CFG_DRAM_TEST)
90 uint
*pstart
= (uint
*) CFG_MEMTEST_START
;
91 uint
*pend
= (uint
*) CFG_MEMTEST_END
;
94 printf("Testing DRAM from 0x%08x to 0x%08x\n",
98 printf("DRAM test phase 1:\n");
99 for (p
= pstart
; p
< pend
; p
++)
102 for (p
= pstart
; p
< pend
; p
++) {
103 if (*p
!= 0xaaaaaaaa) {
104 printf ("DRAM test fails at: %08x\n", (uint
) p
);
109 printf("DRAM test phase 2:\n");
110 for (p
= pstart
; p
< pend
; p
++)
113 for (p
= pstart
; p
< pend
; p
++) {
114 if (*p
!= 0x55555555) {
115 printf ("DRAM test fails at: %08x\n", (uint
) p
);
120 printf("DRAM test passed.\n");
126 static struct pci_controller pci1_hose
;
130 static struct pci_controller pcie1_hose
;
134 static struct pci_controller pcie2_hose
;
138 static struct pci_controller pcie3_hose
;
141 int first_free_busno
=0;
146 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
147 uint devdisr
= gur
->devdisr
;
148 uint io_sel
= (gur
->pordevsr
& MPC85xx_PORDEVSR_IO_SEL
) >> 19;
149 uint host_agent
= (gur
->porbmsr
& MPC85xx_PORBMSR_HA
) >> 16;
151 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
152 devdisr
, io_sel
, host_agent
);
155 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII1_DIS
))
156 printf (" eTSEC1 is in sgmii mode.\n");
157 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
158 printf (" eTSEC3 is in sgmii mode.\n");
163 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCIE3_ADDR
;
164 extern void fsl_pci_init(struct pci_controller
*hose
);
165 struct pci_controller
*hose
= &pcie3_hose
;
166 int pcie_ep
= (host_agent
== 1);
167 int pcie_configured
= io_sel
>= 1;
169 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
170 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
171 pcie_ep
? "End Point" : "Root Complex",
173 if (pci
->pme_msg_det
) {
174 pci
->pme_msg_det
= 0xffffffff;
175 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
180 pci_set_region(hose
->regions
+ 0,
184 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
186 /* outbound memory */
187 pci_set_region(hose
->regions
+ 1,
194 pci_set_region(hose
->regions
+ 2,
200 hose
->region_count
= 3;
201 #ifdef CFG_PCIE3_MEM_BASE2
202 /* outbound memory */
203 pci_set_region(hose
->regions
+ 3,
208 hose
->region_count
++;
210 hose
->first_busno
=first_free_busno
;
211 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
215 first_free_busno
=hose
->last_busno
+1;
216 printf (" PCIE3 on bus %02x - %02x\n",
217 hose
->first_busno
,hose
->last_busno
);
220 * Activate ULI1575 legacy chip by performing a fake
221 * memory access. Needed to make ULI RTC work.
223 in_be32((u32
*)CFG_PCIE3_MEM_BASE
);
225 printf (" PCIE3: disabled\n");
230 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE3
; /* disable */
235 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCIE1_ADDR
;
236 extern void fsl_pci_init(struct pci_controller
*hose
);
237 struct pci_controller
*hose
= &pcie1_hose
;
238 int pcie_ep
= (host_agent
== 5);
239 int pcie_configured
= io_sel
& 6;
241 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
242 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
243 pcie_ep
? "End Point" : "Root Complex",
245 if (pci
->pme_msg_det
) {
246 pci
->pme_msg_det
= 0xffffffff;
247 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
252 pci_set_region(hose
->regions
+ 0,
256 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
258 /* outbound memory */
259 pci_set_region(hose
->regions
+ 1,
266 pci_set_region(hose
->regions
+ 2,
272 hose
->region_count
= 3;
273 #ifdef CFG_PCIE1_MEM_BASE2
274 /* outbound memory */
275 pci_set_region(hose
->regions
+ 3,
280 hose
->region_count
++;
282 hose
->first_busno
=first_free_busno
;
284 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
288 first_free_busno
=hose
->last_busno
+1;
289 printf(" PCIE1 on bus %02x - %02x\n",
290 hose
->first_busno
,hose
->last_busno
);
293 printf (" PCIE1: disabled\n");
298 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE
; /* disable */
303 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCIE2_ADDR
;
304 extern void fsl_pci_init(struct pci_controller
*hose
);
305 struct pci_controller
*hose
= &pcie2_hose
;
306 int pcie_ep
= (host_agent
== 3);
307 int pcie_configured
= io_sel
& 4;
309 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
310 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
311 pcie_ep
? "End Point" : "Root Complex",
313 if (pci
->pme_msg_det
) {
314 pci
->pme_msg_det
= 0xffffffff;
315 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
320 pci_set_region(hose
->regions
+ 0,
324 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
326 /* outbound memory */
327 pci_set_region(hose
->regions
+ 1,
334 pci_set_region(hose
->regions
+ 2,
340 hose
->region_count
= 3;
341 #ifdef CFG_PCIE2_MEM_BASE2
342 /* outbound memory */
343 pci_set_region(hose
->regions
+ 3,
348 hose
->region_count
++;
350 hose
->first_busno
=first_free_busno
;
351 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
354 first_free_busno
=hose
->last_busno
+1;
355 printf (" PCIE2 on bus %02x - %02x\n",
356 hose
->first_busno
,hose
->last_busno
);
359 printf (" PCIE2: disabled\n");
364 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE2
; /* disable */
370 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCI1_ADDR
;
371 extern void fsl_pci_init(struct pci_controller
*hose
);
372 struct pci_controller
*hose
= &pci1_hose
;
374 uint pci_agent
= (host_agent
== 6);
375 uint pci_speed
= 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
377 uint pci_arb
= gur
->pordevsr
& MPC85xx_PORDEVSR_PCI1_ARB
; /* PORDEVSR[14] */
378 uint pci_clk_sel
= gur
->porpllsr
& MPC85xx_PORDEVSR_PCI1_SPD
; /* PORPLLSR[16] */
381 if (!(devdisr
& MPC85xx_DEVDISR_PCI1
)) {
382 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
384 (pci_speed
== 33333000) ? "33" :
385 (pci_speed
== 66666000) ? "66" : "unknown",
386 pci_clk_sel
? "sync" : "async",
387 pci_agent
? "agent" : "host",
388 pci_arb
? "arbiter" : "external-arbiter",
393 pci_set_region(hose
->regions
+ 0,
397 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
399 /* outbound memory */
400 pci_set_region(hose
->regions
+ 1,
407 pci_set_region(hose
->regions
+ 2,
412 hose
->region_count
= 3;
413 #ifdef CFG_PCIE3_MEM_BASE2
414 /* outbound memory */
415 pci_set_region(hose
->regions
+ 3,
420 hose
->region_count
++;
422 hose
->first_busno
=first_free_busno
;
423 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
426 first_free_busno
=hose
->last_busno
+1;
427 printf ("PCI on bus %02x - %02x\n",
428 hose
->first_busno
,hose
->last_busno
);
430 printf (" PCI: disabled\n");
434 gur
->devdisr
|= MPC85xx_DEVDISR_PCI1
; /* disable */
439 int last_stage_init(void)
446 get_board_sys_clk(ulong dummy
)
448 u8 i
, go_bit
, rd_clks
;
451 go_bit
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
454 rd_clks
= in8(PIXIS_BASE
+ PIXIS_VCFGEN0
);
458 * Only if both go bit and the SCLK bit in VCFGEN0 are set
459 * should we be using the AUX register. Remember, we also set the
460 * GO bit to boot from the alternate bank on the on-board flash
465 i
= in8(PIXIS_BASE
+ PIXIS_AUX
);
467 i
= in8(PIXIS_BASE
+ PIXIS_SPD
);
469 i
= in8(PIXIS_BASE
+ PIXIS_SPD
);
504 #if defined(CONFIG_OF_BOARD_SETUP)
507 ft_board_setup(void *blob
, bd_t
*bd
)
512 ft_cpu_setup(blob
, bd
);
514 node
= fdt_path_offset(blob
, "/aliases");
518 path
= fdt_getprop(blob
, node
, "pci0", NULL
);
520 tmp
[1] = pci1_hose
.last_busno
- pci1_hose
.first_busno
;
521 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
525 path
= fdt_getprop(blob
, node
, "pci1", NULL
);
527 tmp
[1] = pcie2_hose
.last_busno
- pcie2_hose
.first_busno
;
528 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
532 path
= fdt_getprop(blob
, node
, "pci2", NULL
);
534 tmp
[1] = pcie1_hose
.last_busno
- pcie1_hose
.first_busno
;
535 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
539 path
= fdt_getprop(blob
, node
, "pci3", NULL
);
541 tmp
[1] = pcie3_hose
.last_busno
- pcie3_hose
.first_busno
;
542 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);