board/freescale/mpc8548cds/mpc8548cds.c

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  *
   4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <asm/processor.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/immap_fsl_pci.h>
  30 #include <spd_sdram.h>
  31 #include <miiphy.h>
  32 #include <libfdt.h>
  33 #include <fdt_support.h>
  34
  35 #include "../common/cadmus.h"
  36 #include "../common/eeprom.h"
  37 #include "../common/via.h"
  38
  39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  40 extern void ddr_enable_ecc(unsigned int dram_size);
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 void local_bus_init(void);
  46 void sdram_init(void);
  47
  48 int checkboard (void)
  49 {
  50         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  51         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
  52
  53         /* PCI slot in USER bits CSR[6:7] by convention. */
  54         uint pci_slot = get_pci_slot ();
  55
  56         uint cpu_board_rev = get_cpu_board_revision ();
  57         uint svr;
  58
  59         printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
  60                 get_board_version (), pci_slot);
  61
  62         printf ("CPU Board Revision %d.%d (0x%04x)\n",
  63                 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  64                 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  65         /*
  66          * Initialize local bus.
  67          */
  68         local_bus_init ();
  69
  70         svr = get_svr();
  71
  72         /*
  73          * Fix CPU2 errata: A core hang possible while executing a
  74          * msync instruction and a snoopable transaction from an I/O
  75          * master tagged to make quick forward progress is present.
  76          * Fixed in Silicon Rev.2.1
  77          */
  78         if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
  79                 ecm->eebpcr |= (1 << 16);
  80
  81         /*
  82          * Hack TSEC 3 and 4 IO voltages.
  83          */
  84         gur->tsec34ioovcr = 0xe7e0;     /*  1110 0111 1110 0xxx */
  85
  86         ecm->eedr = 0xffffffff;         /* clear ecm errors */
  87         ecm->eeer = 0xffffffff;         /* enable ecm errors */
  88         return 0;
  89 }
  90
  91 phys_size_t
  92 initdram(int board_type)
  93 {
  94         long dram_size = 0;
  95
  96         puts("Initializing\n");
  97
  98 #if defined(CONFIG_DDR_DLL)
  99         {
 100                 /*
 101                  * Work around to stabilize DDR DLL MSYNC_IN.
 102                  * Errata DDR9 seems to have been fixed.
 103                  * This is now the workaround for Errata DDR11:
 104                  *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 105                  */
 106
 107                 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 108
 109                 gur->ddrdllcr = 0x81000000;
 110                 asm("sync;isync;msync");
 111                 udelay(200);
 112         }
 113 #endif
 114         dram_size = spd_sdram();
 115
 116 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 117         /*
 118          * Initialize and enable DDR ECC.
 119          */
 120         ddr_enable_ecc(dram_size);
 121 #endif
 122         /*
 123          * SDRAM Initialization
 124          */
 125         sdram_init();
 126
 127         puts("    DDR: ");
 128         return dram_size;
 129 }
 130
 131 /*
 132  * Initialize Local Bus
 133  */
 134 void
 135 local_bus_init(void)
 136 {
 137         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 138         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 139
 140         uint clkdiv;
 141         uint lbc_hz;
 142         sys_info_t sysinfo;
 143
 144         get_sys_info(&sysinfo);
 145         clkdiv = (lbc->lcrr & 0x0f) * 2;
 146         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 147
 148         gur->lbiuiplldcr1 = 0x00078080;
 149         if (clkdiv == 16) {
 150                 gur->lbiuiplldcr0 = 0x7c0f1bf0;
 151         } else if (clkdiv == 8) {
 152                 gur->lbiuiplldcr0 = 0x6c0f1bf0;
 153         } else if (clkdiv == 4) {
 154                 gur->lbiuiplldcr0 = 0x5c0f1bf0;
 155         }
 156
 157         lbc->lcrr |= 0x00030000;
 158
 159         asm("sync;isync;msync");
 160
 161         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
 162         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
 163 }
 164
 165 /*
 166  * Initialize SDRAM memory on the Local Bus.
 167  */
 168 void
 169 sdram_init(void)
 170 {
 171 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 172
 173         uint idx;
 174         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 175         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 176         uint cpu_board_rev;
 177         uint lsdmr_common;
 178
 179         puts("    SDRAM: ");
 180
 181         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 182
 183         /*
 184          * Setup SDRAM Base and Option Registers
 185          */
 186         lbc->or2 = CFG_OR2_PRELIM;
 187         asm("msync");
 188
 189         lbc->br2 = CFG_BR2_PRELIM;
 190         asm("msync");
 191
 192         lbc->lbcr = CFG_LBC_LBCR;
 193         asm("msync");
 194
 195
 196         lbc->lsrt = CFG_LBC_LSRT;
 197         lbc->mrtpr = CFG_LBC_MRTPR;
 198         asm("msync");
 199
 200         /*
 201          * MPC8548 uses "new" 15-16 style addressing.
 202          */
 203         cpu_board_rev = get_cpu_board_revision();
 204         lsdmr_common = CFG_LBC_LSDMR_COMMON;
 205         lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
 206
 207         /*
 208          * Issue PRECHARGE ALL command.
 209          */
 210         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
 211         asm("sync;msync");
 212         *sdram_addr = 0xff;
 213         ppcDcbf((unsigned long) sdram_addr);
 214         udelay(100);
 215
 216         /*
 217          * Issue 8 AUTO REFRESH commands.
 218          */
 219         for (idx = 0; idx < 8; idx++) {
 220                 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
 221                 asm("sync;msync");
 222                 *sdram_addr = 0xff;
 223                 ppcDcbf((unsigned long) sdram_addr);
 224                 udelay(100);
 225         }
 226
 227         /*
 228          * Issue 8 MODE-set command.
 229          */
 230         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
 231         asm("sync;msync");
 232         *sdram_addr = 0xff;
 233         ppcDcbf((unsigned long) sdram_addr);
 234         udelay(100);
 235
 236         /*
 237          * Issue NORMAL OP command.
 238          */
 239         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
 240         asm("sync;msync");
 241         *sdram_addr = 0xff;
 242         ppcDcbf((unsigned long) sdram_addr);
 243         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 244
 245 #endif  /* enable SDRAM init */
 246 }
 247
 248 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
 249 /* For some reason the Tundra PCI bridge shows up on itself as a
 250  * different device.  Work around that by refusing to configure it.
 251  */
 252 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 253
 254 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 255         {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 256         {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
 257         {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 258                 mpc85xx_config_via_usbide, {0,0,0}},
 259         {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
 260                 mpc85xx_config_via_usb, {0,0,0}},
 261         {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
 262                 mpc85xx_config_via_usb2, {0,0,0}},
 263         {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 264                 mpc85xx_config_via_power, {0,0,0}},
 265         {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
 266                 mpc85xx_config_via_ac97, {0,0,0}},
 267         {},
 268 };
 269
 270 static struct pci_controller pci1_hose = {
 271         config_table: pci_mpc85xxcds_config_table};
 272 #endif  /* CONFIG_PCI */
 273
 274 #ifdef CONFIG_PCI2
 275 static struct pci_controller pci2_hose;
 276 #endif  /* CONFIG_PCI2 */
 277
 278 #ifdef CONFIG_PCIE1
 279 static struct pci_controller pcie1_hose;
 280 #endif  /* CONFIG_PCIE1 */
 281
 282 int first_free_busno=0;
 283
 284 void
 285 pci_init_board(void)
 286 {
 287         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 288         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 289         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 290
 291
 292 #ifdef CONFIG_PCI1
 293 {
 294         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 295         extern void fsl_pci_init(struct pci_controller *hose);
 296         struct pci_controller *hose = &pci1_hose;
 297         struct pci_config_table *table;
 298
 299         uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;      /* PORDEVSR[15] */
 300         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 301         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 302
 303         uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
 304
 305         uint pci_speed = get_clock_freq ();     /* PCI PSPEED in [4:5] */
 306
 307         if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
 308                 printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
 309                         (pci_32) ? 32 : 64,
 310                         (pci_speed == 33333000) ? "33" :
 311                         (pci_speed == 66666000) ? "66" : "unknown",
 312                         pci_clk_sel ? "sync" : "async",
 313                         pci_agent ? "agent" : "host",
 314                         pci_arb ? "arbiter" : "external-arbiter"
 315                         );
 316
 317
 318                 /* inbound */
 319                 pci_set_region(hose->regions + 0,
 320                                CFG_PCI_MEMORY_BUS,
 321                                CFG_PCI_MEMORY_PHYS,
 322                                CFG_PCI_MEMORY_SIZE,
 323                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 324
 325
 326                 /* outbound memory */
 327                 pci_set_region(hose->regions + 1,
 328                                CFG_PCI1_MEM_BASE,
 329                                CFG_PCI1_MEM_PHYS,
 330                                CFG_PCI1_MEM_SIZE,
 331                                PCI_REGION_MEM);
 332
 333                 /* outbound io */
 334                 pci_set_region(hose->regions + 2,
 335                                CFG_PCI1_IO_BASE,
 336                                CFG_PCI1_IO_PHYS,
 337                                CFG_PCI1_IO_SIZE,
 338                                PCI_REGION_IO);
 339                 hose->region_count = 3;
 340
 341                 /* relocate config table pointers */
 342                 hose->config_table = \
 343                         (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
 344                 for (table = hose->config_table; table && table->vendor; table++)
 345                         table->config_device += gd->reloc_off;
 346
 347                 hose->first_busno=first_free_busno;
 348                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 349
 350                 fsl_pci_init(hose);
 351                 first_free_busno=hose->last_busno+1;
 352                 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 353 #ifdef CONFIG_PCIX_CHECK
 354                 if (!(gur->pordevsr & PORDEVSR_PCI)) {
 355                         /* PCI-X init */
 356                         if (CONFIG_SYS_CLK_FREQ < 66000000)
 357                                 printf("PCI-X will only work at 66 MHz\n");
 358
 359                         reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 360                                 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 361                         pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
 362                 }
 363 #endif
 364         } else {
 365                 printf ("    PCI: disabled\n");
 366         }
 367 }
 368 #else
 369         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 370 #endif
 371
 372 #ifdef CONFIG_PCI2
 373 {
 374         uint pci2_clk_sel = gur->porpllsr & 0x4000;     /* PORPLLSR[17] */
 375         uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
 376         if (pci_dual) {
 377                 printf ("    PCI2: 32 bit, 66 MHz, %s\n",
 378                         pci2_clk_sel ? "sync" : "async");
 379         } else {
 380                 printf ("    PCI2: disabled\n");
 381         }
 382 }
 383 #else
 384         gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
 385 #endif /* CONFIG_PCI2 */
 386
 387 #ifdef CONFIG_PCIE1
 388 {
 389         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 390         extern void fsl_pci_init(struct pci_controller *hose);
 391         struct pci_controller *hose = &pcie1_hose;
 392         int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
 393
 394         int pcie_configured  = io_sel >= 1;
 395
 396         if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
 397                 printf ("\n    PCIE connected to slot as %s (base address %x)",
 398                         pcie_ep ? "End Point" : "Root Complex",
 399                         (uint)pci);
 400
 401                 if (pci->pme_msg_det) {
 402                         pci->pme_msg_det = 0xffffffff;
 403                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 404                 }
 405                 printf ("\n");
 406
 407                 /* inbound */
 408                 pci_set_region(hose->regions + 0,
 409                                CFG_PCI_MEMORY_BUS,
 410                                CFG_PCI_MEMORY_PHYS,
 411                                CFG_PCI_MEMORY_SIZE,
 412                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 413
 414                 /* outbound memory */
 415                 pci_set_region(hose->regions + 1,
 416                                CFG_PCIE1_MEM_BASE,
 417                                CFG_PCIE1_MEM_PHYS,
 418                                CFG_PCIE1_MEM_SIZE,
 419                                PCI_REGION_MEM);
 420
 421                 /* outbound io */
 422                 pci_set_region(hose->regions + 2,
 423                                CFG_PCIE1_IO_BASE,
 424                                CFG_PCIE1_IO_PHYS,
 425                                CFG_PCIE1_IO_SIZE,
 426                                PCI_REGION_IO);
 427
 428                 hose->region_count = 3;
 429
 430                 hose->first_busno=first_free_busno;
 431                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 432
 433                 fsl_pci_init(hose);
 434                 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
 435
 436                 first_free_busno=hose->last_busno+1;
 437
 438         } else {
 439                 printf ("    PCIE: disabled\n");
 440         }
 441  }
 442 #else
 443         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 444 #endif
 445
 446 }
 447
 448 int last_stage_init(void)
 449 {
 450         unsigned short temp;
 451
 452         /* Change the resistors for the PHY */
 453         /* This is needed to get the RGMII working for the 1.3+
 454          * CDS cards */
 455         if (get_board_version() ==  0x13) {
 456                 miiphy_write(CONFIG_TSEC1_NAME,
 457                                 TSEC1_PHY_ADDR, 29, 18);
 458
 459                 miiphy_read(CONFIG_TSEC1_NAME,
 460                                 TSEC1_PHY_ADDR, 30, &temp);
 461
 462                 temp = (temp & 0xf03f);
 463                 temp |= 2 << 9;         /* 36 ohm */
 464                 temp |= 2 << 6;         /* 39 ohm */
 465
 466                 miiphy_write(CONFIG_TSEC1_NAME,
 467                                 TSEC1_PHY_ADDR, 30, temp);
 468
 469                 miiphy_write(CONFIG_TSEC1_NAME,
 470                                 TSEC1_PHY_ADDR, 29, 3);
 471
 472                 miiphy_write(CONFIG_TSEC1_NAME,
 473                                 TSEC1_PHY_ADDR, 30, 0x8000);
 474         }
 475
 476         return 0;
 477 }
 478
 479
 480 #if defined(CONFIG_OF_BOARD_SETUP)
 481 void
 482 ft_pci_setup(void *blob, bd_t *bd)
 483 {
 484         int node, tmp[2];
 485         const char *path;
 486
 487         node = fdt_path_offset(blob, "/aliases");
 488         tmp[0] = 0;
 489         if (node >= 0) {
 490 #ifdef CONFIG_PCI1
 491                 path = fdt_getprop(blob, node, "pci0", NULL);
 492                 if (path) {
 493                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 494                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 495                 }
 496 #endif
 497 #ifdef CONFIG_PCIE1
 498                 path = fdt_getprop(blob, node, "pci1", NULL);
 499                 if (path) {
 500                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 501                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 502                 }
 503 #endif
 504         }
 505 }
 506 #endif