board/freescale/mpc8548cds/mpc8548cds.c

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  *
   4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <asm/processor.h>
  28 #include <asm/mmu.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <spd_sdram.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36
  37 #include "../common/cadmus.h"
  38 #include "../common/eeprom.h"
  39 #include "../common/via.h"
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 void local_bus_init(void);
  44 void sdram_init(void);
  45
  46 int checkboard (void)
  47 {
  48         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  49         volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  50
  51         /* PCI slot in USER bits CSR[6:7] by convention. */
  52         uint pci_slot = get_pci_slot ();
  53
  54         uint cpu_board_rev = get_cpu_board_revision ();
  55
  56         printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
  57                 get_board_version (), pci_slot);
  58
  59         printf ("CPU Board Revision %d.%d (0x%04x)\n",
  60                 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  61                 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  62         /*
  63          * Initialize local bus.
  64          */
  65         local_bus_init ();
  66
  67         /*
  68          * Hack TSEC 3 and 4 IO voltages.
  69          */
  70         gur->tsec34ioovcr = 0xe7e0;     /*  1110 0111 1110 0xxx */
  71
  72         ecm->eedr = 0xffffffff;         /* clear ecm errors */
  73         ecm->eeer = 0xffffffff;         /* enable ecm errors */
  74         return 0;
  75 }
  76
  77 phys_size_t
  78 initdram(int board_type)
  79 {
  80         long dram_size = 0;
  81
  82         puts("Initializing\n");
  83
  84 #if defined(CONFIG_DDR_DLL)
  85         {
  86                 /*
  87                  * Work around to stabilize DDR DLL MSYNC_IN.
  88                  * Errata DDR9 seems to have been fixed.
  89                  * This is now the workaround for Errata DDR11:
  90                  *    Override DLL = 1, Course Adj = 1, Tap Select = 0
  91                  */
  92
  93                 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  94
  95                 gur->ddrdllcr = 0x81000000;
  96                 asm("sync;isync;msync");
  97                 udelay(200);
  98         }
  99 #endif
 100
 101         dram_size = fsl_ddr_sdram();
 102         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 103         dram_size *= 0x100000;
 104
 105         /*
 106          * SDRAM Initialization
 107          */
 108         sdram_init();
 109
 110         puts("    DDR: ");
 111         return dram_size;
 112 }
 113
 114 /*
 115  * Initialize Local Bus
 116  */
 117 void
 118 local_bus_init(void)
 119 {
 120         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 121         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 122
 123         uint clkdiv;
 124         uint lbc_hz;
 125         sys_info_t sysinfo;
 126
 127         get_sys_info(&sysinfo);
 128         clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 129         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 130
 131         gur->lbiuiplldcr1 = 0x00078080;
 132         if (clkdiv == 16) {
 133                 gur->lbiuiplldcr0 = 0x7c0f1bf0;
 134         } else if (clkdiv == 8) {
 135                 gur->lbiuiplldcr0 = 0x6c0f1bf0;
 136         } else if (clkdiv == 4) {
 137                 gur->lbiuiplldcr0 = 0x5c0f1bf0;
 138         }
 139
 140         lbc->lcrr |= 0x00030000;
 141
 142         asm("sync;isync;msync");
 143
 144         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
 145         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
 146 }
 147
 148 /*
 149  * Initialize SDRAM memory on the Local Bus.
 150  */
 151 void
 152 sdram_init(void)
 153 {
 154 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 155
 156         uint idx;
 157         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 158         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 159         uint cpu_board_rev;
 160         uint lsdmr_common;
 161
 162         puts("    SDRAM: ");
 163
 164         print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 165
 166         /*
 167          * Setup SDRAM Base and Option Registers
 168          */
 169         lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 170         asm("msync");
 171
 172         lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 173         asm("msync");
 174
 175         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 176         asm("msync");
 177
 178
 179         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 180         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 181         asm("msync");
 182
 183         /*
 184          * MPC8548 uses "new" 15-16 style addressing.
 185          */
 186         cpu_board_rev = get_cpu_board_revision();
 187         lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 188         lsdmr_common |= LSDMR_BSMA1516;
 189
 190         /*
 191          * Issue PRECHARGE ALL command.
 192          */
 193         lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 194         asm("sync;msync");
 195         *sdram_addr = 0xff;
 196         ppcDcbf((unsigned long) sdram_addr);
 197         udelay(100);
 198
 199         /*
 200          * Issue 8 AUTO REFRESH commands.
 201          */
 202         for (idx = 0; idx < 8; idx++) {
 203                 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 204                 asm("sync;msync");
 205                 *sdram_addr = 0xff;
 206                 ppcDcbf((unsigned long) sdram_addr);
 207                 udelay(100);
 208         }
 209
 210         /*
 211          * Issue 8 MODE-set command.
 212          */
 213         lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 214         asm("sync;msync");
 215         *sdram_addr = 0xff;
 216         ppcDcbf((unsigned long) sdram_addr);
 217         udelay(100);
 218
 219         /*
 220          * Issue NORMAL OP command.
 221          */
 222         lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 223         asm("sync;msync");
 224         *sdram_addr = 0xff;
 225         ppcDcbf((unsigned long) sdram_addr);
 226         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 227
 228 #endif  /* enable SDRAM init */
 229 }
 230
 231 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
 232 /* For some reason the Tundra PCI bridge shows up on itself as a
 233  * different device.  Work around that by refusing to configure it.
 234  */
 235 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 236
 237 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 238         {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 239         {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
 240         {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 241                 mpc85xx_config_via_usbide, {0,0,0}},
 242         {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
 243                 mpc85xx_config_via_usb, {0,0,0}},
 244         {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
 245                 mpc85xx_config_via_usb2, {0,0,0}},
 246         {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 247                 mpc85xx_config_via_power, {0,0,0}},
 248         {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
 249                 mpc85xx_config_via_ac97, {0,0,0}},
 250         {},
 251 };
 252
 253 static struct pci_controller pci1_hose = {
 254         config_table: pci_mpc85xxcds_config_table};
 255 #endif  /* CONFIG_PCI */
 256
 257 #ifdef CONFIG_PCI2
 258 static struct pci_controller pci2_hose;
 259 #endif  /* CONFIG_PCI2 */
 260
 261 #ifdef CONFIG_PCIE1
 262 static struct pci_controller pcie1_hose;
 263 #endif  /* CONFIG_PCIE1 */
 264
 265 int first_free_busno=0;
 266
 267 void
 268 pci_init_board(void)
 269 {
 270         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 271         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 272         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 273
 274
 275 #ifdef CONFIG_PCI1
 276 {
 277         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 278         struct pci_controller *hose = &pci1_hose;
 279         struct pci_config_table *table;
 280         struct pci_region *r = hose->regions;
 281
 282         uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;      /* PORDEVSR[15] */
 283         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 284         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 285
 286         uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
 287
 288         uint pci_speed = get_clock_freq ();     /* PCI PSPEED in [4:5] */
 289
 290         if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
 291                 printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
 292                         (pci_32) ? 32 : 64,
 293                         (pci_speed == 33333000) ? "33" :
 294                         (pci_speed == 66666000) ? "66" : "unknown",
 295                         pci_clk_sel ? "sync" : "async",
 296                         pci_agent ? "agent" : "host",
 297                         pci_arb ? "arbiter" : "external-arbiter"
 298                         );
 299
 300                 /* outbound memory */
 301                 pci_set_region(r++,
 302                                CONFIG_SYS_PCI1_MEM_BUS,
 303                                CONFIG_SYS_PCI1_MEM_PHYS,
 304                                CONFIG_SYS_PCI1_MEM_SIZE,
 305                                PCI_REGION_MEM);
 306
 307                 /* outbound io */
 308                 pci_set_region(r++,
 309                                CONFIG_SYS_PCI1_IO_BUS,
 310                                CONFIG_SYS_PCI1_IO_PHYS,
 311                                CONFIG_SYS_PCI1_IO_SIZE,
 312                                PCI_REGION_IO);
 313                 hose->region_count = r - hose->regions;
 314
 315                 /* relocate config table pointers */
 316                 hose->config_table = \
 317                         (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
 318                 for (table = hose->config_table; table && table->vendor; table++)
 319                         table->config_device += gd->reloc_off;
 320
 321                 hose->first_busno=first_free_busno;
 322
 323                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 324                 first_free_busno=hose->last_busno+1;
 325                 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 326 #ifdef CONFIG_PCIX_CHECK
 327                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 328                         /* PCI-X init */
 329                         if (CONFIG_SYS_CLK_FREQ < 66000000)
 330                                 printf("PCI-X will only work at 66 MHz\n");
 331
 332                         reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 333                                 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 334                         pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
 335                 }
 336 #endif
 337         } else {
 338                 printf ("    PCI: disabled\n");
 339         }
 340 }
 341 #else
 342         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 343 #endif
 344
 345 #ifdef CONFIG_PCI2
 346 {
 347         uint pci2_clk_sel = gur->porpllsr & 0x4000;     /* PORPLLSR[17] */
 348         uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
 349         if (pci_dual) {
 350                 printf ("    PCI2: 32 bit, 66 MHz, %s\n",
 351                         pci2_clk_sel ? "sync" : "async");
 352         } else {
 353                 printf ("    PCI2: disabled\n");
 354         }
 355 }
 356 #else
 357         gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
 358 #endif /* CONFIG_PCI2 */
 359
 360 #ifdef CONFIG_PCIE1
 361 {
 362         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 363         struct pci_controller *hose = &pcie1_hose;
 364         int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
 365         struct pci_region *r = hose->regions;
 366
 367         int pcie_configured  = io_sel >= 1;
 368
 369         if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
 370                 printf ("\n    PCIE connected to slot as %s (base address %x)",
 371                         pcie_ep ? "End Point" : "Root Complex",
 372                         (uint)pci);
 373
 374                 if (pci->pme_msg_det) {
 375                         pci->pme_msg_det = 0xffffffff;
 376                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 377                 }
 378                 printf ("\n");
 379
 380                 /* outbound memory */
 381                 pci_set_region(r++,
 382                                CONFIG_SYS_PCIE1_MEM_BUS,
 383                                CONFIG_SYS_PCIE1_MEM_PHYS,
 384                                CONFIG_SYS_PCIE1_MEM_SIZE,
 385                                PCI_REGION_MEM);
 386
 387                 /* outbound io */
 388                 pci_set_region(r++,
 389                                CONFIG_SYS_PCIE1_IO_BUS,
 390                                CONFIG_SYS_PCIE1_IO_PHYS,
 391                                CONFIG_SYS_PCIE1_IO_SIZE,
 392                                PCI_REGION_IO);
 393
 394                 hose->region_count = r - hose->regions;
 395
 396                 hose->first_busno=first_free_busno;
 397
 398                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 399                 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
 400
 401                 first_free_busno=hose->last_busno+1;
 402
 403         } else {
 404                 printf ("    PCIE: disabled\n");
 405         }
 406  }
 407 #else
 408         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 409 #endif
 410
 411 }
 412
 413 int last_stage_init(void)
 414 {
 415         unsigned short temp;
 416
 417         /* Change the resistors for the PHY */
 418         /* This is needed to get the RGMII working for the 1.3+
 419          * CDS cards */
 420         if (get_board_version() ==  0x13) {
 421                 miiphy_write(CONFIG_TSEC1_NAME,
 422                                 TSEC1_PHY_ADDR, 29, 18);
 423
 424                 miiphy_read(CONFIG_TSEC1_NAME,
 425                                 TSEC1_PHY_ADDR, 30, &temp);
 426
 427                 temp = (temp & 0xf03f);
 428                 temp |= 2 << 9;         /* 36 ohm */
 429                 temp |= 2 << 6;         /* 39 ohm */
 430
 431                 miiphy_write(CONFIG_TSEC1_NAME,
 432                                 TSEC1_PHY_ADDR, 30, temp);
 433
 434                 miiphy_write(CONFIG_TSEC1_NAME,
 435                                 TSEC1_PHY_ADDR, 29, 3);
 436
 437                 miiphy_write(CONFIG_TSEC1_NAME,
 438                                 TSEC1_PHY_ADDR, 30, 0x8000);
 439         }
 440
 441         return 0;
 442 }
 443
 444
 445 #if defined(CONFIG_OF_BOARD_SETUP)
 446 void ft_pci_setup(void *blob, bd_t *bd)
 447 {
 448 #ifdef CONFIG_PCI1
 449         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 450 #endif
 451 #ifdef CONFIG_PCIE1
 452         ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
 453 #endif
 454 }
 455 #endif