2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright 2002,2003, Motorola Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <ppc_asm.tmpl>
26 #include <asm/cache.h>
33 * TLB0 and TLB1 Entries
35 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
36 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
37 * these TLB entries are established.
39 * The TLB entries for DDR are dynamically setup in spd_sdram()
40 * and use TLB1 Entries 8 through 15 as needed according to the
43 * MAS0: tlbsel, esel, nv
44 * MAS1: valid, iprot, tid, ts, tsize
45 * MAS2: epn, x0, x1, w, i, m, g, e
46 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
59 .section .bootpg, "ax"
65 * Number of TLB0 and TLB1 entries in the following table
69 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
71 * TLB0 4K Non-cacheable, guarded
72 * 0xff700000 4K Initial CCSRBAR mapping
74 * This ends up at a TLB0 Index==0 entry, and must not collide
75 * with other TLB0 Entries.
77 .long FSL_BOOKE_MAS0(0, 0, 0)
78 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
79 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
80 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
82 #error("Update the number of table entries in tlb1_entry")
86 * TLB0 16K Cacheable, non-guarded
87 * 0xd001_0000 16K Temporary Global data for initialization
89 * Use four 4K TLB0 entries. These entries must be cacheable
90 * as they provide the bootstrap memory before the memory
91 * controler and real memory have been configured.
93 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
94 * and must not collide with other TLB0 entries.
96 .long FSL_BOOKE_MAS0(0, 0, 0)
97 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
98 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
99 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
101 .long FSL_BOOKE_MAS0(0, 0, 0)
102 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
103 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
104 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
106 .long FSL_BOOKE_MAS0(0, 0, 0)
107 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
108 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
109 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
111 .long FSL_BOOKE_MAS0(0, 0, 0)
112 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
113 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
114 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
118 * TLB 0: 16M Non-cacheable, guarded
119 * 0xff000000 16M FLASH
120 * Out of reset this entry is only 4K.
122 .long FSL_BOOKE_MAS0(1, 0, 0)
123 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
124 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
125 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
128 * TLB 1: 256M Non-cacheable, guarded
129 * 0x80000000 256M PCI1 MEM First half
131 .long FSL_BOOKE_MAS0(1, 1, 0)
132 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
133 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
134 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
137 * TLB 2: 256M Non-cacheable, guarded
138 * 0x90000000 256M PCI1 MEM Second half
140 .long FSL_BOOKE_MAS0(1, 2, 0)
141 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
142 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
143 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
146 * TLB 3: 256M Non-cacheable, guarded
147 * 0xa0000000 256M PCI2 MEM First half
149 .long FSL_BOOKE_MAS0(1, 3, 0)
150 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
151 .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
152 .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
155 * TLB 4: 256M Non-cacheable, guarded
156 * 0xb0000000 256M PCI2 MEM Second half
158 .long FSL_BOOKE_MAS0(1, 4, 0)
159 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
160 .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
161 .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
164 * TLB 5: 64M Non-cacheable, guarded
165 * 0xe000_0000 1M CCSRBAR
166 * 0xe200_0000 16M PCI1 IO
167 * 0xe300_0000 16M PCI2 IO
169 .long FSL_BOOKE_MAS0(1, 5, 0)
170 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
171 .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
172 .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
175 * TLB 6: 64M Cacheable, non-guarded
176 * 0xf000_0000 64M LBC SDRAM
178 .long FSL_BOOKE_MAS0(1, 6, 0)
179 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
180 .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
181 .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
184 * TLB 7: 1M Non-cacheable, guarded
185 * 0xf8000000 1M CADMUS registers
187 .long FSL_BOOKE_MAS0(1, 7, 0)
188 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
189 .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
190 .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))