board/freescale/mpc8568mds/mpc8568mds.c

   1 /*
   2  * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <asm/processor.h>
  28 #include <asm/mmu.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/fsl_serdes.h>
  33 #include <spd_sdram.h>
  34 #include <i2c.h>
  35 #include <ioports.h>
  36 #include <libfdt.h>
  37 #include <fdt_support.h>
  38
  39 #include "bcsr.h"
  40
  41 const qe_iop_conf_t qe_iop_conf_tab[] = {
  42         /* GETH1 */
  43         {4, 10, 1, 0, 2}, /* TxD0 */
  44         {4,  9, 1, 0, 2}, /* TxD1 */
  45         {4,  8, 1, 0, 2}, /* TxD2 */
  46         {4,  7, 1, 0, 2}, /* TxD3 */
  47         {4, 23, 1, 0, 2}, /* TxD4 */
  48         {4, 22, 1, 0, 2}, /* TxD5 */
  49         {4, 21, 1, 0, 2}, /* TxD6 */
  50         {4, 20, 1, 0, 2}, /* TxD7 */
  51         {4, 15, 2, 0, 2}, /* RxD0 */
  52         {4, 14, 2, 0, 2}, /* RxD1 */
  53         {4, 13, 2, 0, 2}, /* RxD2 */
  54         {4, 12, 2, 0, 2}, /* RxD3 */
  55         {4, 29, 2, 0, 2}, /* RxD4 */
  56         {4, 28, 2, 0, 2}, /* RxD5 */
  57         {4, 27, 2, 0, 2}, /* RxD6 */
  58         {4, 26, 2, 0, 2}, /* RxD7 */
  59         {4, 11, 1, 0, 2}, /* TX_EN */
  60         {4, 24, 1, 0, 2}, /* TX_ER */
  61         {4, 16, 2, 0, 2}, /* RX_DV */
  62         {4, 30, 2, 0, 2}, /* RX_ER */
  63         {4, 17, 2, 0, 2}, /* RX_CLK */
  64         {4, 19, 1, 0, 2}, /* GTX_CLK */
  65         {1, 31, 2, 0, 3}, /* GTX125 */
  66
  67         /* GETH2 */
  68         {5, 10, 1, 0, 2}, /* TxD0 */
  69         {5,  9, 1, 0, 2}, /* TxD1 */
  70         {5,  8, 1, 0, 2}, /* TxD2 */
  71         {5,  7, 1, 0, 2}, /* TxD3 */
  72         {5, 23, 1, 0, 2}, /* TxD4 */
  73         {5, 22, 1, 0, 2}, /* TxD5 */
  74         {5, 21, 1, 0, 2}, /* TxD6 */
  75         {5, 20, 1, 0, 2}, /* TxD7 */
  76         {5, 15, 2, 0, 2}, /* RxD0 */
  77         {5, 14, 2, 0, 2}, /* RxD1 */
  78         {5, 13, 2, 0, 2}, /* RxD2 */
  79         {5, 12, 2, 0, 2}, /* RxD3 */
  80         {5, 29, 2, 0, 2}, /* RxD4 */
  81         {5, 28, 2, 0, 2}, /* RxD5 */
  82         {5, 27, 2, 0, 3}, /* RxD6 */
  83         {5, 26, 2, 0, 2}, /* RxD7 */
  84         {5, 11, 1, 0, 2}, /* TX_EN */
  85         {5, 24, 1, 0, 2}, /* TX_ER */
  86         {5, 16, 2, 0, 2}, /* RX_DV */
  87         {5, 30, 2, 0, 2}, /* RX_ER */
  88         {5, 17, 2, 0, 2}, /* RX_CLK */
  89         {5, 19, 1, 0, 2}, /* GTX_CLK */
  90         {1, 31, 2, 0, 3}, /* GTX125 */
  91         {4,  6, 3, 0, 2}, /* MDIO */
  92         {4,  5, 1, 0, 2}, /* MDC */
  93
  94         /* UART1 */
  95         {2, 0, 1, 0, 2}, /* UART_SOUT1 */
  96         {2, 1, 1, 0, 2}, /* UART_RTS1 */
  97         {2, 2, 2, 0, 2}, /* UART_CTS1 */
  98         {2, 3, 2, 0, 2}, /* UART_SIN1 */
  99
 100         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
 101 };
 102
 103 void local_bus_init(void);
 104 void sdram_init(void);
 105
 106 int board_early_init_f (void)
 107 {
 108         /*
 109          * Initialize local bus.
 110          */
 111         local_bus_init ();
 112
 113         enable_8568mds_duart();
 114         enable_8568mds_flash_write();
 115 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
 116         reset_8568mds_uccs();
 117 #endif
 118 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
 119         enable_8568mds_qe_mdio();
 120 #endif
 121
 122 #ifdef CONFIG_SYS_I2C2_OFFSET
 123         /* Enable I2C2_SCL and I2C2_SDA */
 124         volatile struct par_io *port_c;
 125         port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
 126         port_c->cpdir2 |= 0x0f000000;
 127         port_c->cppar2 &= ~0x0f000000;
 128         port_c->cppar2 |= 0x0a000000;
 129 #endif
 130
 131         return 0;
 132 }
 133
 134 int checkboard (void)
 135 {
 136         printf ("Board: 8568 MDS\n");
 137
 138         return 0;
 139 }
 140
 141 phys_size_t
 142 initdram(int board_type)
 143 {
 144         long dram_size = 0;
 145
 146         puts("Initializing\n");
 147
 148 #if defined(CONFIG_DDR_DLL)
 149         {
 150                 /*
 151                  * Work around to stabilize DDR DLL MSYNC_IN.
 152                  * Errata DDR9 seems to have been fixed.
 153                  * This is now the workaround for Errata DDR11:
 154                  *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 155                  */
 156
 157                 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 158
 159                 gur->ddrdllcr = 0x81000000;
 160                 asm("sync;isync;msync");
 161                 udelay(200);
 162         }
 163 #endif
 164
 165         dram_size = fsl_ddr_sdram();
 166         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 167         dram_size *= 0x100000;
 168
 169         /*
 170          * SDRAM Initialization
 171          */
 172         sdram_init();
 173
 174         puts("    DDR: ");
 175         return dram_size;
 176 }
 177
 178 /*
 179  * Initialize Local Bus
 180  */
 181 void
 182 local_bus_init(void)
 183 {
 184         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 185         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 186
 187         uint clkdiv;
 188         uint lbc_hz;
 189         sys_info_t sysinfo;
 190
 191         get_sys_info(&sysinfo);
 192         clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 193         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 194
 195         gur->lbiuiplldcr1 = 0x00078080;
 196         if (clkdiv == 16) {
 197                 gur->lbiuiplldcr0 = 0x7c0f1bf0;
 198         } else if (clkdiv == 8) {
 199                 gur->lbiuiplldcr0 = 0x6c0f1bf0;
 200         } else if (clkdiv == 4) {
 201                 gur->lbiuiplldcr0 = 0x5c0f1bf0;
 202         }
 203
 204         lbc->lcrr |= 0x00030000;
 205
 206         asm("sync;isync;msync");
 207 }
 208
 209 /*
 210  * Initialize SDRAM memory on the Local Bus.
 211  */
 212 void
 213 sdram_init(void)
 214 {
 215 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 216
 217         uint idx;
 218         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 219         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 220         uint lsdmr_common;
 221
 222         puts("    SDRAM: ");
 223
 224         print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 225
 226         /*
 227          * Setup SDRAM Base and Option Registers
 228          */
 229         set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 230         set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 231         asm("msync");
 232
 233         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 234         asm("msync");
 235
 236         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 237         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 238         asm("msync");
 239
 240         /*
 241          * MPC8568 uses "new" 15-16 style addressing.
 242          */
 243         lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 244         lsdmr_common |= LSDMR_BSMA1516;
 245
 246         /*
 247          * Issue PRECHARGE ALL command.
 248          */
 249         lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 250         asm("sync;msync");
 251         *sdram_addr = 0xff;
 252         ppcDcbf((unsigned long) sdram_addr);
 253         udelay(100);
 254
 255         /*
 256          * Issue 8 AUTO REFRESH commands.
 257          */
 258         for (idx = 0; idx < 8; idx++) {
 259                 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 260                 asm("sync;msync");
 261                 *sdram_addr = 0xff;
 262                 ppcDcbf((unsigned long) sdram_addr);
 263                 udelay(100);
 264         }
 265
 266         /*
 267          * Issue 8 MODE-set command.
 268          */
 269         lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 270         asm("sync;msync");
 271         *sdram_addr = 0xff;
 272         ppcDcbf((unsigned long) sdram_addr);
 273         udelay(100);
 274
 275         /*
 276          * Issue NORMAL OP command.
 277          */
 278         lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 279         asm("sync;msync");
 280         *sdram_addr = 0xff;
 281         ppcDcbf((unsigned long) sdram_addr);
 282         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 283
 284 #endif  /* enable SDRAM init */
 285 }
 286
 287 #if defined(CONFIG_PCI)
 288 #ifndef CONFIG_PCI_PNP
 289 static struct pci_config_table pci_mpc8568mds_config_table[] = {
 290         {
 291          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 292          pci_cfgfunc_config_device,
 293          {PCI_ENET0_IOADDR,
 294           PCI_ENET0_MEMADDR,
 295           PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
 296          },
 297         {}
 298 };
 299 #endif
 300
 301 static struct pci_controller pci1_hose = {
 302 #ifndef CONFIG_PCI_PNP
 303         config_table: pci_mpc8568mds_config_table,
 304 #endif
 305 };
 306 #endif  /* CONFIG_PCI */
 307
 308 #ifdef CONFIG_PCIE1
 309 static struct pci_controller pcie1_hose;
 310 #endif  /* CONFIG_PCIE1 */
 311
 312 /*
 313  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
 314  */
 315 void
 316 pib_init(void)
 317 {
 318         u8 val8, orig_i2c_bus;
 319         /*
 320          * Assign PIB PMC2/3 to PCI bus
 321          */
 322
 323         /*switch temporarily to I2C bus #2 */
 324         orig_i2c_bus = i2c_get_bus_num();
 325         i2c_set_bus_num(1);
 326
 327         val8 = 0x00;
 328         i2c_write(0x23, 0x6, 1, &val8, 1);
 329         i2c_write(0x23, 0x7, 1, &val8, 1);
 330         val8 = 0xff;
 331         i2c_write(0x23, 0x2, 1, &val8, 1);
 332         i2c_write(0x23, 0x3, 1, &val8, 1);
 333
 334         val8 = 0x00;
 335         i2c_write(0x26, 0x6, 1, &val8, 1);
 336         val8 = 0x34;
 337         i2c_write(0x26, 0x7, 1, &val8, 1);
 338         val8 = 0xf9;
 339         i2c_write(0x26, 0x2, 1, &val8, 1);
 340         val8 = 0xff;
 341         i2c_write(0x26, 0x3, 1, &val8, 1);
 342
 343         val8 = 0x00;
 344         i2c_write(0x27, 0x6, 1, &val8, 1);
 345         i2c_write(0x27, 0x7, 1, &val8, 1);
 346         val8 = 0xff;
 347         i2c_write(0x27, 0x2, 1, &val8, 1);
 348         val8 = 0xef;
 349         i2c_write(0x27, 0x3, 1, &val8, 1);
 350
 351         asm("eieio");
 352 }
 353
 354 #ifdef CONFIG_PCI
 355 void pci_init_board(void)
 356 {
 357         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 358         struct fsl_pci_info pci_info[2];
 359         u32 devdisr, pordevsr, io_sel;
 360         u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 361         int first_free_busno = 0;
 362         int num = 0;
 363
 364         int pcie_ep, pcie_configured;
 365
 366         devdisr = in_be32(&gur->devdisr);
 367         pordevsr = in_be32(&gur->pordevsr);
 368         porpllsr = in_be32(&gur->porpllsr);
 369         io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 370
 371         debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 372
 373 #ifdef CONFIG_PCI1
 374         pci_speed = 66666000;
 375         pci_32 = 1;
 376         pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 377         pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 378
 379         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 380                 SET_STD_PCI_INFO(pci_info[num], 1);
 381                 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
 382                 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 383                         (pci_32) ? 32 : 64,
 384                         (pci_speed == 33333000) ? "33" :
 385                         (pci_speed == 66666000) ? "66" : "unknown",
 386                         pci_clk_sel ? "sync" : "async",
 387                         pci_agent ? "agent" : "host",
 388                         pci_arb ? "arbiter" : "external-arbiter",
 389                         pci_info[num].regs);
 390
 391                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 392                                         &pci1_hose, first_free_busno);
 393         } else {
 394                 printf("PCI: disabled\n");
 395         }
 396
 397         puts("\n");
 398 #else
 399         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 400 #endif
 401
 402 #ifdef CONFIG_PCIE1
 403         pcie_configured = is_serdes_configured(PCIE1);
 404
 405         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 406                 SET_STD_PCIE_INFO(pci_info[num], 1);
 407                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 408                 printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
 409                                 pcie_ep ? "Endpoint" : "Root Complex",
 410                                 pci_info[num].regs);
 411
 412                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 413                                         &pcie1_hose, first_free_busno);
 414         } else {
 415                 printf("PCIE1: disabled\n");
 416         }
 417
 418         puts("\n");
 419 #else
 420         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 421 #endif
 422 }
 423 #endif /* CONFIG_PCI */
 424
 425 #if defined(CONFIG_OF_BOARD_SETUP)
 426 void ft_board_setup(void *blob, bd_t *bd)
 427 {
 428         ft_cpu_setup(blob, bd);
 429
 430         FT_FSL_PCI_SETUP;
 431 }
 432 #endif