board/freescale/mpc8569mds/bcsr.c

   1 /*
   2  * Copyright (C) 2009 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9
  10 #include "bcsr.h"
  11
  12 void enable_8569mds_flash_write(void)
  13 {
  14         setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
  15 }
  16
  17 void disable_8569mds_flash_write(void)
  18 {
  19         clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
  20 }
  21
  22 void enable_8569mds_qe_uec(void)
  23 {
  24 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  25         setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
  26                         BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
  27         setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
  28                         BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
  29         setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
  30                         BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
  31         setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
  32                         BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
  33 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  34         /* Set UCC1-4 working at RMII mode */
  35         clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
  36                         BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
  37         clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
  38                         BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
  39         clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
  40                         BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
  41         clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
  42                         BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
  43         setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
  44 #endif
  45 }
  46
  47 void disable_8569mds_brd_eeprom_write_protect(void)
  48 {
  49         clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
  50 }