1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2009 Freescale Semiconductor, Inc.
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
11 void fsl_ddr_board_options(memctl_options_t
*popts
,
13 unsigned int ctrl_num
)
16 * Factors to consider for clock adjust:
17 * - number of chips on bus
22 * This needs to be determined on a board-by-board basis.
26 popts
->clk_adjust
= 4;
29 * Factors to consider for CPO:
33 popts
->cpo_override
= 0xff;
36 * Factors to consider for write data delay:
46 popts
->write_data_delay
= 2;
49 * Enable half drive strength
51 popts
->half_strength_driver_enable
= 1;
53 /* Write leveling override */
55 popts
->wrlvl_override
= 1;
56 popts
->wrlvl_sample
= 0xa;
57 popts
->wrlvl_start
= 0x4;
59 /* Rtt and Rtt_W override */
60 popts
->rtt_override
= 1;
61 popts
->rtt_override_value
= DDR3_RTT_60_OHM
;
62 popts
->rtt_wr_override_value
= 0; /* Rtt_WR= dynamic ODT off */