board/freescale/mpc8569mds/mpc8569mds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2010 Freescale Semiconductor.
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <console.h>
  10 #include <hwconfig.h>
  11 #include <pci.h>
  12 #include <asm/processor.h>
  13 #include <asm/mmu.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_pci.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/io.h>
  20 #include <spd_sdram.h>
  21 #include <i2c.h>
  22 #include <ioports.h>
  23 #include <linux/libfdt.h>
  24 #include <fdt_support.h>
  25 #include <fsl_esdhc.h>
  26 #include <phy.h>
  27
  28 #include "bcsr.h"
  29 #if defined(CONFIG_PQ_MDS_PIB)
  30 #include "../common/pq-mds-pib.h"
  31 #endif
  32
  33 const qe_iop_conf_t qe_iop_conf_tab[] = {
  34         /* QE_MUX_MDC */
  35         {2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
  36
  37         /* QE_MUX_MDIO */
  38         {2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
  39
  40 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  41         /* UCC_1_RGMII */
  42         {2, 11, 2, 0, 1}, /* CLK12 */
  43         {0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
  44         {0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
  45         {0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
  46         {0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
  47         {0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
  48         {0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
  49         {0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
  50         {0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
  51         {0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
  52         {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
  53         {2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
  54         {2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */
  55
  56         /* UCC_2_RGMII */
  57         {2, 16, 2, 0, 3}, /* CLK17 */
  58         {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
  59         {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
  60         {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
  61         {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
  62         {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
  63         {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
  64         {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
  65         {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
  66         {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
  67         {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
  68         {2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
  69         {2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
  70
  71         /* UCC_3_RGMII */
  72         {2, 11, 2, 0, 1}, /* CLK12 */
  73         {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
  74         {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
  75         {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
  76         {1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
  77         {1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
  78         {1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
  79         {1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
  80         {1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
  81         {1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
  82         {1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
  83         {2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
  84         {2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
  85
  86         /* UCC_4_RGMII */
  87         {2, 16, 2, 0, 3}, /* CLK17 */
  88         {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
  89         {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
  90         {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
  91         {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
  92         {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
  93         {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
  94         {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
  95         {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
  96         {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
  97         {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
  98         {2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
  99         {2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
 100
 101 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 102         /* UCC_1_RMII */
 103         {2, 15, 2, 0, 1}, /* CLK16 */
 104         {0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
 105         {0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
 106         {0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
 107         {0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
 108         {0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
 109         {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
 110
 111         /* UCC_2_RMII */
 112         {2, 15, 2, 0, 1}, /* CLK16 */
 113         {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
 114         {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
 115         {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
 116         {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
 117         {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
 118         {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
 119
 120         /* UCC_3_RMII */
 121         {2, 15, 2, 0, 1}, /* CLK16 */
 122         {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
 123         {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
 124         {1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
 125         {1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
 126         {1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
 127         {1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
 128
 129         /* UCC_4_RMII */
 130         {2, 15, 2, 0, 1}, /* CLK16 */
 131         {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
 132         {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
 133         {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
 134         {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
 135         {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
 136         {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
 137 #endif
 138
 139         /* UART1 is muxed with QE PortF bit [9-12].*/
 140         {5, 12, 2, 0, 3}, /* UART1_SIN */
 141         {5, 9,  1, 0, 3}, /* UART1_SOUT */
 142         {5, 10, 2, 0, 3}, /* UART1_CTS_B */
 143         {5, 11, 1, 0, 2}, /* UART1_RTS_B */
 144
 145         /* QE UART                                     */
 146         {0, 19, 1, 0, 2}, /* QEUART_TX                 */
 147         {1, 17, 2, 0, 3}, /* QEUART_RX                 */
 148         {0, 25, 1, 0, 1}, /* QEUART_RTS                */
 149         {1, 23, 2, 0, 1}, /* QEUART_CTS                */
 150
 151         /* QE USB                                      */
 152         {5,  3, 1, 0, 1}, /* USB_OE                    */
 153         {5,  4, 1, 0, 2}, /* USB_TP                    */
 154         {5,  5, 1, 0, 2}, /* USB_TN                    */
 155         {5,  6, 2, 0, 2}, /* USB_RP                    */
 156         {5,  7, 2, 0, 1}, /* USB_RX                    */
 157         {5,  8, 2, 0, 1}, /* USB_RN                    */
 158         {2,  4, 2, 0, 2}, /* CLK5                      */
 159
 160         /* SPI Flash, M25P40                           */
 161         {4, 27, 3, 0, 1}, /* SPI_MOSI                  */
 162         {4, 28, 3, 0, 1}, /* SPI_MISO                  */
 163         {4, 29, 3, 0, 1}, /* SPI_CLK                   */
 164         {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */
 165
 166         {0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 167 };
 168
 169 void local_bus_init(void);
 170
 171 int board_early_init_f (void)
 172 {
 173         /*
 174          * Initialize local bus.
 175          */
 176         local_bus_init ();
 177
 178         enable_8569mds_flash_write();
 179
 180 #ifdef CONFIG_QE
 181         enable_8569mds_qe_uec();
 182 #endif
 183
 184 #if CONFIG_SYS_I2C2_OFFSET
 185         /* Enable I2C2 signals instead of SD signals */
 186         volatile struct ccsr_gur *gur;
 187         gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
 188         gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
 189         gur->plppar1 |= PLPPAR1_I2C2_VAL;
 190         gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
 191         gur->plpdir1 |= PLPDIR1_I2C2_VAL;
 192
 193         disable_8569mds_brd_eeprom_write_protect();
 194 #endif
 195
 196         return 0;
 197 }
 198
 199 int board_early_init_r(void)
 200 {
 201         const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
 202         const u8 flash_esel = 0;
 203
 204         /*
 205          * Remap Boot flash to caching-inhibited
 206          * so that flash can be erased properly.
 207          */
 208
 209         /* Flush d-cache and invalidate i-cache of any FLASH data */
 210         flush_dcache();
 211         invalidate_icache();
 212
 213         /* invalidate existing TLB entry for flash */
 214         disable_tlb(flash_esel);
 215
 216         set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,     /* tlb, epn, rpn */
 217                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 218                 0, flash_esel,                          /* ts, esel */
 219                 BOOKE_PAGESZ_64M, 1);                   /* tsize, iprot */
 220
 221         return 0;
 222 }
 223
 224 int checkboard (void)
 225 {
 226         printf ("Board: 8569 MDS\n");
 227
 228         return 0;
 229 }
 230
 231 #if !defined(CONFIG_SPD_EEPROM)
 232 phys_size_t fixed_sdram(void)
 233 {
 234         struct ccsr_ddr __iomem *ddr =
 235                 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 236         uint d_init;
 237
 238         out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
 239         out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
 240         out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
 241         out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
 242         out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
 243         out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
 244         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
 245         out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
 246         out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
 247         out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
 248         out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
 249         out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
 250         out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
 251         out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
 252         out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
 253         out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
 254         out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
 255         out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
 256 #if defined (CONFIG_DDR_ECC)
 257         out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
 258         out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
 259         out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
 260 #endif
 261         udelay(500);
 262
 263         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
 264 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 265         d_init = 1;
 266         debug("DDR - 1st controller: memory initializing\n");
 267         /*
 268          * Poll until memory is initialized.
 269          * 512 Meg at 400 might hit this 200 times or so.
 270          */
 271         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 272                 udelay(1000);
 273         }
 274         debug("DDR: memory initialized\n\n");
 275         udelay(500);
 276 #endif
 277         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 278 }
 279 #endif
 280
 281 /*
 282  * Initialize Local Bus
 283  */
 284 void
 285 local_bus_init(void)
 286 {
 287         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 288         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 289
 290         uint clkdiv;
 291         sys_info_t sysinfo;
 292
 293         get_sys_info(&sysinfo);
 294         clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 295
 296         out_be32(&gur->lbiuiplldcr1, 0x00078080);
 297         if (clkdiv == 16)
 298                 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
 299         else if (clkdiv == 8)
 300                 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
 301         else if (clkdiv == 4)
 302                 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
 303
 304         out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
 305 }
 306
 307 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
 308 {
 309         const char *status = "disabled";
 310         int off;
 311         int err;
 312
 313         off = fdt_path_offset(blob, alias);
 314         if (off < 0) {
 315                 printf("WARNING: could not find %s alias: %s.\n", alias,
 316                         fdt_strerror(off));
 317                 return;
 318         }
 319
 320         err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
 321         if (err) {
 322                 printf("WARNING: could not set status for serial0: %s.\n",
 323                         fdt_strerror(err));
 324                 return;
 325         }
 326 }
 327
 328 /*
 329  * Because of an erratum in prototype boards it is impossible to use eSDHC
 330  * without disabling UART0 (which makes it quite easy to 'brick' the board
 331  * by simply issung 'setenv hwconfig esdhc', and not able to interact with
 332  * U-Boot anylonger).
 333  *
 334  * So, but default we assume that the board is a prototype, which is a most
 335  * safe assumption. There is no way to determine board revision from a
 336  * register, so we use hwconfig.
 337  */
 338
 339 static int prototype_board(void)
 340 {
 341         if (hwconfig_subarg("board", "rev", NULL))
 342                 return hwconfig_subarg_cmp("board", "rev", "prototype");
 343         return 1;
 344 }
 345
 346 static int esdhc_disables_uart0(void)
 347 {
 348         return prototype_board() ||
 349                hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
 350 }
 351
 352 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
 353 {
 354         u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
 355         const char *devtype = "serial";
 356         const char *compat = "ucc_uart";
 357         const char *clk = "brg9";
 358         u32 portnum = 0;
 359         int off = -1;
 360
 361         if (!hwconfig("qe_uart"))
 362                 return;
 363
 364         if (hwconfig("esdhc") && esdhc_disables_uart0()) {
 365                 printf("QE UART: won't enable with esdhc.\n");
 366                 return;
 367         }
 368
 369         fdt_board_disable_serial(blob, bd, "serial1");
 370
 371         while (1) {
 372                 const u32 *idx;
 373                 int len;
 374
 375                 off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
 376                 if (off < 0) {
 377                         printf("WARNING: unable to fixup device tree for "
 378                                 "QE UART\n");
 379                         return;
 380                 }
 381
 382                 idx = fdt_getprop(blob, off, "cell-index", &len);
 383                 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
 384                         continue;
 385                 break;
 386         }
 387
 388         fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
 389         fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
 390         fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
 391         fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
 392         fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
 393
 394         setbits_8(&bcsr[15], BCSR15_QEUART_EN);
 395 }
 396
 397 #ifdef CONFIG_FSL_ESDHC
 398
 399 int board_mmc_init(bd_t *bd)
 400 {
 401         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 402         u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
 403         u8 bcsr6 = BCSR6_SD_CARD_1BIT;
 404
 405         if (!hwconfig("esdhc"))
 406                 return 0;
 407
 408         printf("Enabling eSDHC...\n"
 409                "  For eSDHC to function, I2C2 ");
 410         if (esdhc_disables_uart0()) {
 411                 printf("and UART0 should be disabled.\n");
 412                 printf("  Redirecting stderr, stdout and stdin to UART1...\n");
 413                 console_assign(stderr, "eserial1");
 414                 console_assign(stdout, "eserial1");
 415                 console_assign(stdin, "eserial1");
 416                 printf("Switched to UART1 (initial log has been printed to "
 417                        "UART0).\n");
 418
 419                 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
 420                                                PLPPAR1_ESDHC_4BITS_VAL);
 421                 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
 422                                                PLPDIR1_ESDHC_4BITS_VAL);
 423                 bcsr6 |= BCSR6_SD_CARD_4BITS;
 424         } else {
 425                 printf("should be disabled.\n");
 426         }
 427
 428         /* Assign I2C2 signals to eSDHC. */
 429         clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
 430                                        PLPPAR1_ESDHC_VAL);
 431         clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
 432                                        PLPDIR1_ESDHC_VAL);
 433
 434         /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
 435         setbits_8(&bcsr[6], bcsr6);
 436
 437         return fsl_esdhc_mmc_init(bd);
 438 }
 439
 440 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
 441 {
 442         const char *status = "disabled";
 443         int off = -1;
 444
 445         if (!hwconfig("esdhc"))
 446                 return;
 447
 448         if (esdhc_disables_uart0())
 449                 fdt_board_disable_serial(blob, bd, "serial0");
 450
 451         while (1) {
 452                 const u32 *idx;
 453                 int len;
 454
 455                 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
 456                 if (off < 0)
 457                         break;
 458
 459                 idx = fdt_getprop(blob, off, "cell-index", &len);
 460                 if (!idx || len != sizeof(*idx))
 461                         continue;
 462
 463                 if (*idx == 1) {
 464                         fdt_setprop(blob, off, "status", status,
 465                                     strlen(status) + 1);
 466                         break;
 467                 }
 468         }
 469
 470         if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
 471                 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
 472                 if (off < 0) {
 473                         printf("WARNING: could not find esdhc node\n");
 474                         return;
 475                 }
 476                 fdt_delprop(blob, off, "sdhci,1-bit-only");
 477         }
 478 }
 479 #else
 480 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
 481 #endif
 482
 483 static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
 484 {
 485         u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
 486
 487         if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
 488                 clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
 489         else
 490                 setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
 491
 492         if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
 493                 clrbits_8(&bcsr[17], BCSR17_USBVCC);
 494                 clrbits_8(&bcsr[17], BCSR17_USBMODE);
 495                 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
 496                                    "peripheral", sizeof("peripheral"), 1);
 497         } else {
 498                 setbits_8(&bcsr[17], BCSR17_USBVCC);
 499                 setbits_8(&bcsr[17], BCSR17_USBMODE);
 500         }
 501
 502         clrbits_8(&bcsr[17], BCSR17_nUSBEN);
 503 }
 504
 505 #ifdef CONFIG_PCI
 506 void pci_init_board(void)
 507 {
 508 #if defined(CONFIG_PQ_MDS_PIB)
 509         pib_init();
 510 #endif
 511
 512         fsl_pcie_init_board(0);
 513 }
 514 #endif /* CONFIG_PCI */
 515
 516 #if defined(CONFIG_OF_BOARD_SETUP)
 517 int ft_board_setup(void *blob, bd_t *bd)
 518 {
 519 #if defined(CONFIG_SYS_UCC_RMII_MODE)
 520         int nodeoff, off, err;
 521         unsigned int val;
 522         const u32 *ph;
 523         const u32 *index;
 524
 525         /* fixup device tree for supporting rmii mode */
 526         nodeoff = -1;
 527         while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
 528                                 "ucc_geth")) >= 0) {
 529                 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
 530                                                 "clk16");
 531                 if (err < 0) {
 532                         printf("WARNING: could not set tx-clock-name %s.\n",
 533                                 fdt_strerror(err));
 534                         break;
 535                 }
 536
 537                 err = fdt_fixup_phy_connection(blob, nodeoff,
 538                                 PHY_INTERFACE_MODE_RMII);
 539
 540                 if (err < 0) {
 541                         printf("WARNING: could not set phy-connection-type "
 542                                 "%s.\n", fdt_strerror(err));
 543                         break;
 544                 }
 545
 546                 index = fdt_getprop(blob, nodeoff, "cell-index", 0);
 547                 if (index == NULL) {
 548                         printf("WARNING: could not get cell-index of ucc\n");
 549                         break;
 550                 }
 551
 552                 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
 553                 if (ph == NULL) {
 554                         printf("WARNING: could not get phy-handle of ucc\n");
 555                         break;
 556                 }
 557
 558                 off = fdt_node_offset_by_phandle(blob, *ph);
 559                 if (off < 0) {
 560                         printf("WARNING: could not get phy node %s.\n",
 561                                 fdt_strerror(err));
 562                         break;
 563                 }
 564
 565                 val = 0x7 + *index; /* RMII phy address starts from 0x8 */
 566
 567                 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
 568                 if (err < 0) {
 569                         printf("WARNING: could not set reg for phy-handle "
 570                                 "%s.\n", fdt_strerror(err));
 571                         break;
 572                 }
 573         }
 574 #endif
 575         ft_cpu_setup(blob, bd);
 576
 577         FT_FSL_PCI_SETUP;
 578
 579         fdt_board_fixup_esdhc(blob, bd);
 580         fdt_board_fixup_qe_uart(blob, bd);
 581         fdt_board_fixup_qe_usb(blob, bd);
 582
 583         return 0;
 584 }
 585 #endif