board/freescale/mpc8569mds/mpc8569mds.c

   1 /*
   2  * Copyright 2009 Freescale Semiconductor.
   3  *
   4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <hwconfig.h>
  27 #include <pci.h>
  28 #include <asm/processor.h>
  29 #include <asm/mmu.h>
  30 #include <asm/immap_85xx.h>
  31 #include <asm/fsl_pci.h>
  32 #include <asm/fsl_ddr_sdram.h>
  33 #include <asm/io.h>
  34 #include <spd_sdram.h>
  35 #include <i2c.h>
  36 #include <ioports.h>
  37 #include <libfdt.h>
  38 #include <fdt_support.h>
  39 #include <fsl_esdhc.h>
  40
  41 #include "bcsr.h"
  42
  43 phys_size_t fixed_sdram(void);
  44
  45 const qe_iop_conf_t qe_iop_conf_tab[] = {
  46         /* QE_MUX_MDC */
  47         {2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
  48
  49         /* QE_MUX_MDIO */
  50         {2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
  51
  52 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  53         /* UCC_1_RGMII */
  54         {2, 11, 2, 0, 1}, /* CLK12 */
  55         {0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
  56         {0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
  57         {0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
  58         {0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
  59         {0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
  60         {0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
  61         {0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
  62         {0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
  63         {0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
  64         {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
  65         {2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
  66         {2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */
  67
  68         /* UCC_2_RGMII */
  69         {2, 16, 2, 0, 3}, /* CLK17 */
  70         {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
  71         {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
  72         {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
  73         {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
  74         {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
  75         {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
  76         {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
  77         {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
  78         {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
  79         {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
  80         {2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
  81         {2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
  82
  83         /* UCC_3_RGMII */
  84         {2, 11, 2, 0, 1}, /* CLK12 */
  85         {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
  86         {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
  87         {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
  88         {1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
  89         {1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
  90         {1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
  91         {1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
  92         {1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
  93         {1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
  94         {1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
  95         {2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
  96         {2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
  97
  98         /* UCC_4_RGMII */
  99         {2, 16, 2, 0, 3}, /* CLK17 */
 100         {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
 101         {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
 102         {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
 103         {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
 104         {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
 105         {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
 106         {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
 107         {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
 108         {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
 109         {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
 110         {2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
 111         {2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
 112
 113 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 114         /* UCC_1_RMII */
 115         {2, 15, 2, 0, 1}, /* CLK16 */
 116         {0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
 117         {0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
 118         {0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
 119         {0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
 120         {0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
 121         {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
 122
 123         /* UCC_2_RMII */
 124         {2, 15, 2, 0, 1}, /* CLK16 */
 125         {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
 126         {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
 127         {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
 128         {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
 129         {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
 130         {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
 131
 132         /* UCC_3_RMII */
 133         {2, 15, 2, 0, 1}, /* CLK16 */
 134         {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
 135         {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
 136         {1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
 137         {1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
 138         {1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
 139         {1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
 140
 141         /* UCC_4_RMII */
 142         {2, 15, 2, 0, 1}, /* CLK16 */
 143         {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
 144         {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
 145         {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
 146         {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
 147         {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
 148         {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
 149 #endif
 150
 151         /* UART1 is muxed with QE PortF bit [9-12].*/
 152         {5, 12, 2, 0, 3}, /* UART1_SIN */
 153         {5, 9,  1, 0, 3}, /* UART1_SOUT */
 154         {5, 10, 2, 0, 3}, /* UART1_CTS_B */
 155         {5, 11, 1, 0, 2}, /* UART1_RTS_B */
 156
 157         /* SPI Flash, M25P40                           */
 158         {4, 27, 3, 0, 1}, /* SPI_MOSI                  */
 159         {4, 28, 3, 0, 1}, /* SPI_MISO                  */
 160         {4, 29, 3, 0, 1}, /* SPI_CLK                   */
 161         {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */
 162
 163         {0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 164 };
 165
 166 void local_bus_init(void);
 167
 168 int board_early_init_f (void)
 169 {
 170         /*
 171          * Initialize local bus.
 172          */
 173         local_bus_init ();
 174
 175         enable_8569mds_flash_write();
 176
 177 #ifdef CONFIG_QE
 178         enable_8569mds_qe_uec();
 179 #endif
 180
 181 #if CONFIG_SYS_I2C2_OFFSET
 182         /* Enable I2C2 signals instead of SD signals */
 183         volatile struct ccsr_gur *gur;
 184         gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
 185         gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
 186         gur->plppar1 |= PLPPAR1_I2C2_VAL;
 187         gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
 188         gur->plpdir1 |= PLPDIR1_I2C2_VAL;
 189
 190         disable_8569mds_brd_eeprom_write_protect();
 191 #endif
 192
 193         return 0;
 194 }
 195
 196 int checkboard (void)
 197 {
 198         printf ("Board: 8569 MDS\n");
 199
 200         return 0;
 201 }
 202
 203 phys_size_t
 204 initdram(int board_type)
 205 {
 206         long dram_size = 0;
 207
 208         puts("Initializing\n");
 209
 210 #if defined(CONFIG_DDR_DLL)
 211         /*
 212          * Work around to stabilize DDR DLL MSYNC_IN.
 213          * Errata DDR9 seems to have been fixed.
 214          * This is now the workaround for Errata DDR11:
 215          *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 216          */
 217         volatile ccsr_gur_t *gur =
 218                         (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 219
 220         out_be32(&gur->ddrdllcr, 0x81000000);
 221         udelay(200);
 222 #endif
 223
 224 #ifdef CONFIG_SPD_EEPROM
 225         dram_size = fsl_ddr_sdram();
 226 #else
 227         dram_size = fixed_sdram();
 228 #endif
 229
 230         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 231         dram_size *= 0x100000;
 232
 233         puts("    DDR: ");
 234         return dram_size;
 235 }
 236
 237 #if !defined(CONFIG_SPD_EEPROM)
 238 phys_size_t fixed_sdram(void)
 239 {
 240         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 241         uint d_init;
 242
 243         out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
 244         out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
 245         out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
 246         out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
 247         out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
 248         out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
 249         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
 250         out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
 251         out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
 252         out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
 253         out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
 254         out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
 255         out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
 256         out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
 257         out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
 258         out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
 259         out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
 260         out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
 261 #if defined (CONFIG_DDR_ECC)
 262         out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
 263         out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
 264         out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
 265 #endif
 266         udelay(500);
 267
 268         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
 269 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 270         d_init = 1;
 271         debug("DDR - 1st controller: memory initializing\n");
 272         /*
 273          * Poll until memory is initialized.
 274          * 512 Meg at 400 might hit this 200 times or so.
 275          */
 276         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 277                 udelay(1000);
 278         }
 279         debug("DDR: memory initialized\n\n");
 280         udelay(500);
 281 #endif
 282         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 283 }
 284 #endif
 285
 286 /*
 287  * Initialize Local Bus
 288  */
 289 void
 290 local_bus_init(void)
 291 {
 292         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 293         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 294
 295         uint clkdiv;
 296         uint lbc_hz;
 297         sys_info_t sysinfo;
 298
 299         get_sys_info(&sysinfo);
 300         clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 301         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 302
 303         out_be32(&gur->lbiuiplldcr1, 0x00078080);
 304         if (clkdiv == 16)
 305                 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
 306         else if (clkdiv == 8)
 307                 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
 308         else if (clkdiv == 4)
 309                 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
 310
 311         out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
 312 }
 313
 314 #ifdef CONFIG_FSL_ESDHC
 315
 316 /*
 317  * Because of an erratum in prototype boards it is impossible to use eSDHC
 318  * without disabling UART0 (which makes it quite easy to 'brick' the board
 319  * by simply issung 'setenv hwconfig esdhc', and not able to interact with
 320  * U-Boot anylonger).
 321  *
 322  * So, but default we assume that the board is a prototype, which is a most
 323  * safe assumption. There is no way to determine board revision from a
 324  * register, so we use hwconfig.
 325  */
 326
 327 static int prototype_board(void)
 328 {
 329         if (hwconfig_subarg("board", "rev", NULL))
 330                 return hwconfig_subarg_cmp("board", "rev", "prototype");
 331         return 1;
 332 }
 333
 334 static int esdhc_disables_uart0(void)
 335 {
 336         return prototype_board() ||
 337                hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
 338 }
 339
 340 int board_mmc_init(bd_t *bd)
 341 {
 342         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 343         u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
 344         u8 bcsr6 = BCSR6_SD_CARD_1BIT;
 345
 346         if (!hwconfig("esdhc"))
 347                 return 0;
 348
 349         printf("Enabling eSDHC...\n"
 350                "  For eSDHC to function, I2C2 ");
 351         if (esdhc_disables_uart0()) {
 352                 printf("and UART0 should be disabled.\n");
 353                 printf("  Redirecting stderr, stdout and stdin to UART1...\n");
 354                 console_assign(stderr, "eserial1");
 355                 console_assign(stdout, "eserial1");
 356                 console_assign(stdin, "eserial1");
 357                 printf("Switched to UART1 (initial log has been printed to "
 358                        "UART0).\n");
 359                 bcsr6 |= BCSR6_SD_CARD_4BITS;
 360         } else {
 361                 printf("should be disabled.\n");
 362         }
 363
 364         /* Assign I2C2 signals to eSDHC. */
 365         clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
 366                                        PLPPAR1_ESDHC_VAL);
 367         clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
 368                                        PLPDIR1_ESDHC_VAL);
 369
 370         /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
 371         setbits_8(&bcsr[6], bcsr6);
 372
 373         return fsl_esdhc_mmc_init(bd);
 374 }
 375
 376 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
 377 {
 378         const char *status = "disabled";
 379         int off;
 380         int err;
 381
 382         if (!hwconfig("esdhc"))
 383                 return;
 384
 385         if (!esdhc_disables_uart0())
 386                 goto disable_i2c2;
 387
 388         off = fdt_path_offset(blob, "serial0");
 389         if (off < 0) {
 390                 printf("WARNING: could not find serial0 alias: %s.\n",
 391                         fdt_strerror(off));
 392                 goto disable_i2c2;
 393         }
 394
 395         err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
 396         if (err) {
 397                 printf("WARNING: could not set status for serial0: %s.\n",
 398                         fdt_strerror(err));
 399                 return;
 400         }
 401
 402 disable_i2c2:
 403         off = -1;
 404         while (1) {
 405                 const u32 *idx;
 406                 int len;
 407
 408                 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
 409                 if (off < 0)
 410                         break;
 411
 412                 idx = fdt_getprop(blob, off, "cell-index", &len);
 413                 if (!idx || len != sizeof(*idx))
 414                         continue;
 415
 416                 if (*idx == 1) {
 417                         fdt_setprop(blob, off, "status", status,
 418                                     strlen(status) + 1);
 419                         break;
 420                 }
 421         }
 422 }
 423 #else
 424 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
 425 #endif
 426
 427 #ifdef CONFIG_PCIE1
 428 static struct pci_controller pcie1_hose;
 429 #endif  /* CONFIG_PCIE1 */
 430
 431 int first_free_busno = 0;
 432
 433 #ifdef CONFIG_PCI
 434 void
 435 pci_init_board(void)
 436 {
 437         volatile ccsr_gur_t *gur;
 438         uint io_sel;
 439         uint host_agent;
 440
 441         gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 442         io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 443         host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 444
 445 #ifdef CONFIG_PCIE1
 446 {
 447         volatile ccsr_fsl_pci_t *pci;
 448         struct pci_controller *hose;
 449         int pcie_ep;
 450         struct pci_region *r;
 451         int pcie_configured;
 452
 453         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 454         hose = &pcie1_hose;
 455         pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
 456         r = hose->regions;
 457         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 458
 459         if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
 460                 printf ("\n    PCIE connected to slot as %s (base address %x)",
 461                         pcie_ep ? "End Point" : "Root Complex",
 462                         (uint)pci);
 463
 464                 if (pci->pme_msg_det) {
 465                         pci->pme_msg_det = 0xffffffff;
 466                         debug (" with errors.  Clearing. Now 0x%08x",
 467                                 pci->pme_msg_det);
 468                 }
 469                 printf ("\n");
 470
 471                 /* outbound memory */
 472                 pci_set_region(r++,
 473                                 CONFIG_SYS_PCIE1_MEM_BUS,
 474                                 CONFIG_SYS_PCIE1_MEM_PHYS,
 475                                 CONFIG_SYS_PCIE1_MEM_SIZE,
 476                                 PCI_REGION_MEM);
 477
 478                 /* outbound io */
 479                 pci_set_region(r++,
 480                                 CONFIG_SYS_PCIE1_IO_BUS,
 481                                 CONFIG_SYS_PCIE1_IO_PHYS,
 482                                 CONFIG_SYS_PCIE1_IO_SIZE,
 483                                 PCI_REGION_IO);
 484
 485                 hose->region_count = r - hose->regions;
 486
 487                 hose->first_busno=first_free_busno;
 488
 489                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 490                 printf ("PCIE on bus %02x - %02x\n",
 491                                 hose->first_busno,hose->last_busno);
 492
 493                 first_free_busno=hose->last_busno+1;
 494
 495         } else {
 496                 printf ("    PCIE: disabled\n");
 497         }
 498 }
 499 #else
 500         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 501 #endif
 502 }
 503 #endif /* CONFIG_PCI */
 504
 505 #if defined(CONFIG_OF_BOARD_SETUP)
 506 void ft_board_setup(void *blob, bd_t *bd)
 507 {
 508 #if defined(CONFIG_SYS_UCC_RMII_MODE)
 509         int nodeoff, off, err;
 510         unsigned int val;
 511         const u32 *ph;
 512         const u32 *index;
 513
 514         /* fixup device tree for supporting rmii mode */
 515         nodeoff = -1;
 516         while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
 517                                 "ucc_geth")) >= 0) {
 518                 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
 519                                                 "clk16");
 520                 if (err < 0) {
 521                         printf("WARNING: could not set tx-clock-name %s.\n",
 522                                 fdt_strerror(err));
 523                         break;
 524                 }
 525
 526                 err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
 527                                         "rmii");
 528                 if (err < 0) {
 529                         printf("WARNING: could not set phy-connection-type "
 530                                 "%s.\n", fdt_strerror(err));
 531                         break;
 532                 }
 533
 534                 index = fdt_getprop(blob, nodeoff, "cell-index", 0);
 535                 if (index == NULL) {
 536                         printf("WARNING: could not get cell-index of ucc\n");
 537                         break;
 538                 }
 539
 540                 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
 541                 if (ph == NULL) {
 542                         printf("WARNING: could not get phy-handle of ucc\n");
 543                         break;
 544                 }
 545
 546                 off = fdt_node_offset_by_phandle(blob, *ph);
 547                 if (off < 0) {
 548                         printf("WARNING: could not get phy node %s.\n",
 549                                 fdt_strerror(err));
 550                         break;
 551                 }
 552
 553                 val = 0x7 + *index; /* RMII phy address starts from 0x8 */
 554
 555                 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
 556                 if (err < 0) {
 557                         printf("WARNING: could not set reg for phy-handle "
 558                                 "%s.\n", fdt_strerror(err));
 559                         break;
 560                 }
 561         }
 562 #endif
 563         ft_cpu_setup(blob, bd);
 564
 565 #ifdef CONFIG_PCIE1
 566         ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
 567 #endif
 568         fdt_board_fixup_esdhc(blob, bd);
 569 }
 570 #endif